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Wiki source code of 05 Registers

Version 2.6 by Leo Wei on 2022/07/28 11:27
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Leo Wei 1.1 1 (% class="box infomessage" %)
2 (((
3 **The following table lists all the devices that WECON LX3V series PLC supports.**
4 )))
5
6 Table 1
7
8 (% border="2" class="table-bordered" %)
9 |=(% style="width: 58px;" %)**No.**|=(% style="width: 263px;" %)**Device**|=(% style="width: 761px;" %)**Descriptions**
10 |(% style="width:58px" %)1|(% style="width:263px" %)X - Input|(% style="width:761px" %)Representation of physical inputs to PLC;
11 |(% style="width:58px" %)2|(% style="width:263px" %)Y - Output|(% style="width:761px" %)Representation of physical outputs from PLC;
12 |(% style="width:58px" %)3|(% style="width:263px" %)M - Intermediate|(% style="width:761px" %)(((
13 Common intermediate register; System special register;
14 )))
15
16 (% class="table-bordered" %)
17 |=(% style="width: 58px;" %)4|=(% style="width: 268px;" %)S - State|=(% style="width: 756px;" %)PLC internal states flag for step control;
18 |(% style="width:58px" %)5|(% style="width:268px" %)T - Timer|(% style="width:756px" %)16-bit timer (1, 10 and 100ms)
19 |(% style="width:58px" %)6|(% style="width:268px" %)C - Counter|(% style="width:756px" %)(((
20 16-bit and 32-bit up/down counter; High speed counter;
21 )))
22 |(% style="width:58px" %)7|(% style="width:268px" %)D – Data register|(% style="width:756px" %)(((
23 Data register; String register; Indirect addressing address;
24 )))
25 |(% style="width:58px" %)8|(% style="width:268px" %)P, I - Pointer|(% style="width:756px" %)(((
26 Jump pointer; Sub-program pointer; Interrupt pointer (high speed, );
27 )))
28 |(% style="width:58px" %)9|(% style="width:268px" %)K, H - Constant|(% style="width:756px" %)Binary, decimal, hexadecimal, floating point, etc.
29
30 Table 2
31
32 (% border="2" class="table-bordered" %)
33 |=**Device**|=**LX3V(1S firmware)**|=**LX3V (2N firmware)**|=**LX3VP**|=**LX3VE**|=**Expansion module**
34 |X - input|X0~~X13 (Max. 12)|X0~~X43 (Max. 36)|X0~~X43 (Max. 36)|X0~~X43 (Max. 36)|X0~~X77 (Max.128)
35 |Y - output|Y0~~Y7 (Max. 8)|Y0~~Y27 (Max. 24)|Y0~~Y27 (Max. 24)|Y0~~Y27 (Max. 24)|Y0~~Y77 (Max.128)
36
37 = **5.1 Relay X & Y** =
38
39 == **5.1.1 Input relay X** ==
40
41 The input relay X represents the physical inputs to PLC. It could detect the external signal states. 0 is for open circuit, 1 is for closed circuit.
42
43 The states of input relays couldn’t be modified by program instruction, the node signal (normally open, normally closed) could be unlimited use in the program.
44
45 If connected IO** **expansion module, the port starts from the main module, according to the order of the numbers. But DI is named in groups of eight. For example main module is X0~~X7, X10~~X14. The X0 in DI expansion module corresponds to X20, not X15.
46
47 Devices numbered in: Octal, i.e. X0 to X7, X10 to X17
48
49 **~ [Available devices]**
50
51 Table 1
52
53 (% class="table-bordered" %)
54 |=**Model**|=**Input**|=**Output**|=**Model**|=**Input**|=**Output**
55 |LX3V-0806MR/MT-A1(D1)|X0~~X7|Y0~~Y5|LX3VP-1208MR/MT-A(D)|X0~~X7|Y0~~Y5
56 |LX3V-1208MR/MT-A1(D1)|X0~~X13|Y0~~Y7|LX3VP-1212MR/MT-A(D)|X0~~X13|Y0~~Y13
57 |LX3V-0806MR/MT-A2(D2)|X0~~X7|Y0~~Y5|LX3VP-1412MR/MT-A(D)|X0~~X15|Y0~~Y13
58 |LX3V-1208MR/MT-A2(D2)|X0~~X13|Y0~~Y7|LX3VP-1616MR/MT-A(D)|X0~~X17|Y0~~Y17
59 |LX3V-1212MR/MT-A(D)|X0~~X13|Y0~~Y13|LX3VP-2416MR/MT-A(D)|X0~~X27|Y0~~Y17
60 |LX3V-1410MR/MT-A(D)|X0~~X15|Y0~~Y11|LX3VP-2424MR/MT-A(D)|X0~~X27|Y0~~Y27
61 |LX3V-1412MR/MT-A(D)|X0~~X15|Y0~~Y13|LX3VP-3624MR/MT-A(D)|X0~~X43|Y0~~Y27
62 |LX3V-1616MR/MT-A(D)|X0~~X17|Y0~~Y17|LX3VE-1412MR/MT-A(D)|X0~~X15|Y0~~Y13
63 |LX3V-2416MR/MT-A(D)|X0~~X27|Y0~~Y17|LX3VE-1616MR/MT-A(D)|X0~~X17|Y0~~Y17
64 |LX3V-2424MR/MT-A(D)|X0~~X27|Y0~~Y27|LX3VE-2416MR/MT-A(D)|X0~~X27|Y0~~Y17
65 |LX3V-3624MR/MT-A(D)|X0~~X43|Y0~~Y27|LX3VE-2424MR/MT-A(D)|X0~~X27|Y0~~Y27
66 | | | |LX3VE-3624MR/MT-A(D)|X0~~X43|Y0~~Y27
67
68 == **5.1.2 Output replay Y** ==
69
70 The output relay Y represents physical outputs from PLC. 0 is for open circuit, 1 is for closed circuit.
71
72 Depending on the output element could be divided into relay type, transistor type etc.
73
74 If connected IO** **expansion module, the port starts from the main module, according to the order of the numbers. But DO is named in groups of eight. For example main module is Y0~~Y7, Y10~~Y14. The Y0 in DO expansion module corresponds to Y20, not Y15.
75
76 Devices numbered in: Octal, i.e. Y0 to Y7, Y10 to Y17.
77
78 = **5.2 Relays M** =
79
80 Auxiliary Relay M device is used as an intermediate variable during the execution of a program, as auxiliary relays in the practical power control system which is used to transfer the state messages. It could use the word variable formed by M variables. M variables is not directly linked with any external ports, but it could contact with the outside world by the manners of copying X to M or M to Y through the program coding. A variable M could be used repeatedly.
81
82 Devices numbered in: Decimal, i.e. M0 to M9, M10 to M19. The variables that are more than M8000 are the system-specific variables, which are used to interact with the PLC user program with the system states; part of the M variables have the feature of power-saving.
83
84 == **5.2.1 General Stable State Auxiliary Relays** ==
85
86 The general stable state Auxiliary relays in LX3V series PLC are M0 ~~ M499, there are total of 500 points. The type of auxiliary relay is related to its part number and PLC serial.
87
88 Table 1
89
90 (% class="table-bordered" %)
91 |=(% style="width: 217px;" %)**PLC**|=(% style="width: 181px;" %)**General**|=(% style="width: 208px;" %)**Latched**|=(% style="width: 238px;" %)**Latched-specific**|=(% style="width: 238px;" %)**System-specific**
92 |(% style="width:217px" %)LX3V (1S firmware)|(% style="width:181px" %)(((
93 384 ※3
94
95 (M0 – M383)
96 )))|(% style="width:208px" %)-|(% style="width:238px" %)(((
97 128 ※3
98
99 (M383 – M511)
100 )))|(% style="width:238px" %)(((
101 256
102
103 (M8000-M8255)
104 )))
105 |(% style="width:217px" %)LX3V (2N firmware)|(% style="width:181px" %)(((
106 500 ※1
107
108 (M0 – M499)
109 )))|(% style="width:208px" %)(((
110 524 ※ 2
111
112 (M500 – M1023)
113 )))|(% style="width:238px" %)(((
114 2048 ※3
115
116 (M1024 – M3071)
117 )))|(% style="width:238px" %)(((
118 256
119
120 (M8000-M8255)
121 )))
122 |(% style="width:217px" %)LX3VP|(% style="width:181px" %)(((
123 500 ※1
124
125 (M0 – M499)
126 )))|(% style="width:208px" %)(((
127 524 ※ 2
128
129 (M500 – M1023)
130 )))|(% style="width:238px" %)(((
131 2048 ※3
132
133 (M1024 – M3071)
134 )))|(% style="width:238px" %)(((
135 256
136
137 (M8000-M8255)
138 )))
139 |(% style="width:217px" %)LX3VE|(% style="width:181px" %)(((
140 500 ※1
141
142 (M0 – M499)
143 )))|(% style="width:208px" %)(((
144 524 ※ 2
145
146 (M500 – M1023)
147 )))|(% style="width:238px" %)(((
148 2048 ※3
149
150 (M1024 – M3071)
151 )))|(% style="width:238px" %)(((
152 256
153
154 (M8000-M8255)
155 )))
156
157 Users could set non-latched and latched area for Auxiliary relays in PLC by parameter setting
158
159 ※1, Non-latched area, it could be changed to latched area by parameter setting.
160
161 ※2, Latched area, it could be changed to non-latched area by parameter setting.
162
163 ※3, The non-latched or latched feature couldn’t be changed.
164
165 == **5.2.2 Latched auxiliary relays** ==
166
167 There are a number of latched relays whose state is retained. If a power failure should occur all output and general purpose relays are switched off. When operation is resumed the previous state of these relays is restored.
168
169 As below pictures show, in (a), relay M500 is activated when X0 is turned ON. If X0 is turned OFF after the activation of M500, the ON state of M500 is self-retained. (b) shows Circuit Waveform diagram of (a). For using this function, (c) could makes M500 “Turn ON” all the time.
170
171 (% style="text-align:center" %)
172 [[image:1650081615924-404.png||class="img-thumbnail" height="107" width="600"]]
173
174 == **5.2.3 System-specific auxiliary relays** ==
175
176 A PLC has a number of special auxiliary relays. These relays all have specific functions such as provide clock pulse and sign, set PLC operation mode, or use for step control, prohibit interrupt, set counter is adding count or subtract count, etc. And they are classified into the following two types.
177
178 * Using contacts of special auxiliary relays, coils are driven automatically by the PLC. Only the contacts of these coils may be used by a user defined program.
179 **Examples:**
180 ** M8000: RUN monitor (ON during run);
181 ** M8002: Initial pulse (Turned ON momentarily when PLC starts);
182 ** M8012: 100 msec clock pulse;
183
184 * Driving coils of special auxiliary relays, a PLC executes a predetermined specific operation when these coils are driven by the user.
185
186 **~ Examples:**
187
188 *
189 ** M8033: All output statuses are retained when PLC operation is stopped;
190 ** M8034: All outputs are disabled;
191 ** M8039: The PLC operates under constant scould mode;
192
193 = **5.3 Relays S** =
194
195 State relays S is used to design and handle step procedures, controls transfer of step by STL step instructions to simplify programming design. S also could be used as M, if there is no STL instruction. Part of the S has the feature of power-saving.
196
197 Devices numbered in: Decimal, i.e. S0 to S9, S10 to S19.
198
199 Table 1
200
201 (% class="table-bordered" %)
202 |=(% rowspan="2" %)**PLC**|=(% colspan="3" %)**General**|=(% colspan="3" %)**Latched**|=(% rowspan="2" %)**Alarm**
203 |**-**|**Initialized**|**-**|**-**|**Initialized**|**-**
204 |LX3V (1S firmware)|-|-|-|(((
205 128 ※3
206
207 (S0 – S127)
208 )))|(((
209 10
210
211 (S0 – S9)
212 )))|(((
213 10
214
215 (S10 –S19)
216 )))|
217 |LX3V (2N firmware)|(((
218 500 ※1
219
220 (S0 – S499)
221 )))|(((
222 10
223
224 (S0 – S9)
225 )))|(((
226 10
227
228 (S10 – S19)
229 )))|(((
230 400 ※2
231
232 (S500 – S899)
233 )))|-|-|(((
234 100 ※2
235
236 (S900 – S999)
237 )))
238 |LX3VP|(((
239 500 ※1
240
241 (S0 – S499)
242 )))|(((
243 10
244
245 (S0 – S9)
246 )))|(((
247 10
248
249 (S10 – S19)
250 )))|(((
251 400 ※2
252
253 (S500 – S899)
254 )))|-|-|(((
255 100 ※2
256
257 (S900 – S999)
258 )))
259 |LX3VE|(((
260 500 ※1
261
262 (S0 – S499)
263 )))|(((
264 10
265
266 (S0 – S9)
267 )))|(((
268 10
269
270 (S10 – S19)
271 )))|(((
272 400 ※2
273
274 (S500 – S899)
275 )))|-|-|(((
276 100 ※2
277
278 (S900 – S999)
279 )))
280
281 ※1, Non-latched area, it could be changed to latched area by parameter setting.
282
283 ※2, Latched area, it could be changed to non-latched area by parameter setting.
284
285 ※3, The non-latched or latched feature couldn’t be changed.
286
287 == **5.3.1 General State Relays** ==
288
289 As above picture shows, when X0=ON, then S0 set ON, and Y0 is activated. When X1=ON, then S11 set ON, and Y1 is activated. When X2=ON, S12 set ON, then Y2 is activated, as Figure 3-2 shows.
290
291 == **5.3.2 Latched State Relays** ==
292
293 There are a number of latched relays whose state is retained. If a power failure should occur all output and general purpose relays are switched off. When operation is resumed the previous state of these relays is restored.
294
295 [[image:file:///C:/Users/Administrator/AppData/Local/Temp/ksohtml13508/wps31.jpg||alt="file:///C:\Users\Administrator\AppData\Local\Temp\ksohtml13508\wps31.jpg"]]
296
297 Figure 2
298
299 (% style="text-align:center" %)
300 [[image:1650087341412-765.png||class="img-thumbnail" height="392" width="500"]]
301
302 == **5.3.3 Annunciator Flags** ==
303
304 Some state flags could be used as outputs for external diagnosis (called annunciation) when certain applied instructions are used.
305
306 (% style="text-align:center" %)
307 [[image:1650087434137-885.png||class="img-thumbnail" height="84" width="400"]]
308
309 If X1 and X2 set ON at the same time and keep more than 1 seconds, S900 is activated, if X1 or X2 is turned OFF after the activation of S900, the ON state of S900 is self-retained. If X1 and X2 set ON at the same time less than 1 seconds, S900 is not activated.
310
311 = **5.4 Timer** =
312
313 The timer is used to perform the timing function. Each timer contains coils, contacts, and counting time value register. A driven coil sets internal PLC contacts. Various timer resolutions are possible, from 1 to 100ms. If the coil power shuts off (insufficient power), the contacts will restore to their initial states and the value will automatically be cleared. Some timers have the feature of accumulation and power-saving.
314
315 Devices numbered in: Decimal, i.e. T0 to T9, T10 to T19.
316
317 Table 1
318
319 (% class="table-bordered" %)
320 |=(% style="width: 162px;" %)**PLC**|=(% style="width: 168px;" %)(((
321 **100ms**
322
323 **0.1– 3276.7s**
324 )))|=(% style="width: 168px;" %)(((
325 **100ms**
326
327 **0.1 – 3276.7s**
328
329 **0.01–327.67s**
330 )))|=(% style="width: 176px;" %)(((
331 **10ms**
332
333 **0.01-327.67s**
334 )))|=(% style="width: 184px;" %)(((
335 **Retentive 1ms**
336
337 **0.001-32.767s**
338 )))|=(% style="width: 224px;" %)(((
339 **Retentive 100ms**
340
341 **0.1–3276.7s**
342 )))
343 |(% style="width:162px" %)LX3V (1S Firmware)|(% style="width:168px" %)(((
344 32
345
346 (T0 – T31)
347 )))|(% style="width:168px" %)(((
348 31
349
350 (T32 – T62)
351 )))|(% style="width:176px" %)(((
352 31
353
354 (T32 – T62)
355 )))|(% style="width:184px" %)(((
356 1
357
358 (T63)
359 )))|(% style="width:224px" %)
360 |(% rowspan="2" style="width:162px" %)LX3V (2N Firmware)|(% style="width:168px" %)(((
361 200
362
363 (T0 – T199)
364 )))|(% rowspan="2" style="width:168px" %)-|(% rowspan="2" style="width:176px" %)(((
365 46
366
367 (T200 – T245)
368 )))|(% rowspan="2" style="width:184px" %)(((
369 Interrupted 4
370
371 (T246 – T249)
372 )))|(% rowspan="2" style="width:224px" %)(((
373 6
374
375 (T250 – T255)
376 )))
377 |(% style="width:168px" %)(((
378 Sub-program 8
379
380 (T192–T199)
381 )))
382 |(% rowspan="2" style="width:162px" %)LX3VP|(% style="width:168px" %)(((
383 200
384
385 (T0 – T199)
386 )))|(% rowspan="2" style="width:168px" %)-|(% rowspan="2" style="width:176px" %)(((
387 46
388
389 (T200 – T245)
390 )))|(% rowspan="2" style="width:184px" %)(((
391 Interrupted 4
392
393 (T246 – T249)
394 )))|(% rowspan="2" style="width:224px" %)(((
395 6
396
397 (T250 – T255)
398 )))
399 |(% style="width:168px" %)(((
400 Sub-program 8
401
402 (T192–T199)
403 )))
404 |(% rowspan="2" style="width:162px" %)LX3VE|(% style="width:168px" %)(((
405 200
406
407 (T0 – T199)
408 )))|(% rowspan="2" style="width:168px" %)-|(% rowspan="2" style="width:176px" %)(((
409 46
410
411 (T200 – T245)
412 )))|(% rowspan="2" style="width:184px" %)(((
413 Interrupted 4
414
415 (T246 – T249)
416 )))|(% rowspan="2" style="width:224px" %)(((
417 6
418
419 (T250 – T255)
420 )))
421 |(% style="width:168px" %)(((
422 Sub-program 8
423
424 (T192–T199)
425 )))
426
427 == **5.4.1 General timer (T0~~T245)** ==
428
429 The timer output contact is activated when the count data reaches the value set by the constant K.
430
431 (% style="text-align:center" %)
432 [[image:1650087703091-787.png||class="img-thumbnail" height="133" width="500"]]
433
434 Figure 2
435
436 As above picture shows, when X0 is on, T200 counts from zero and accumulates 10ms clock pulses. When the current value is equal to the set value 223, timer output contact is activated; the output contact of the T200 is actuated after its coil is driven by 2.23s.
437
438 == **5.4.2 Retentive Timers (T246~~T255)** ==
439
440 (% style="text-align:center" %)
441 [[image:1650087743260-243.png||class="img-thumbnail" height="150" width="500"]]
442
443 Figure 3
444
445 As above picture shows, T250 has the ability to retain the currently reached present value even after X1 has been removed. If T1+T2=42s, T250 (open contact) set on. When X2 set ON, timer T250 will be reset.
446
447 == **5.4.3 Set value** ==
448
449 The set value of the timer could be determined by constant (K, H) in the program memory and could also be specified indirectly with the contents of the data register (D).
450
451 (% style="text-align:center" %)
452 [[image:1650087806303-500.png||class="img-thumbnail" height="176" width="400"]]
453
454 As above program shows, D3 is set value for T10, D3=D0*2.
455
456 = **5.5 Counter** =
457
458 == **5.5.1 Counter** ==
459
460 Counter performs counting function, it contains coil, contact and count value register. The current value of the counter increases each time coil C0 is turned ON. The output contact is activated when count value reach to preset value.
461
462 Counters which are latched are able to retain their status information, even after the PLC has been powered down. This means on re-powering up, the latched counters could immediately resume from where they were at the time of the original PLC power down.
463
464 Devices numbered in: Decimal, i.e. C0 to C9, C10 to C19
465
466 Table 1
467
468 (% class="table-bordered" %)
469 |=(% rowspan="2" %)**PLC**|=(% colspan="2" %)(((
470 **16bit UP Counters**
471
472 **0 – 32,767**
473 )))|=(% colspan="2" %)(((
474 **32bit Bi-directional Counters  -2,147,483,648 - +2,147483647**
475 )))
476 |**General**|**Latched**|**General**|**Latched**
477 |LX1S|16 (C0 – C15) ※3|16 (C16 – C31) ※3|-|-
478 |LX2N|100 (C0-C99) ※1|100(C100 – C199) ※2|20 (C200 – C219) ※1|15 (C220 – C234) ※2
479 |LX3V|100 (C0-C99) ※1|100(C100 – C199) ※2|20 (C200 – C219) ※1|15 (C220 – C234) ※2
480
481 ※1, Non-latched area, it could be changed to latched area by parameter setting.
482
483 ※2, Latched area, it could be changed to non-latched area by parameter setting.
484
485 ※3, The non-latched or latched feature couldn’t be changed.
486
487 === **5.5.1.1 16bit up counter** ===
488
489 16bit counters: 1 to +32,767, as below picture shows, the current value of the counter increases each time coil C0 is turned ON by X2. The output contact is activated when the coil is turned ON for the tenth time.
490
491 After this, the counter data remains unchanged when X2 is turned ON. The counter current value is reset to ‘0’ (zero) when the RST instruction is executed by turning ON X1 in the example. The output contact Y0 is also reset at the same time.
492
493 (% style="text-align:center" %)
494 [[image:1650088012596-185.png||class="img-thumbnail" height="169" width="500"]]
495
496 Figure 2
497
498 === **5.5.1.2 32bit bi-directional counter** ===
499
500 32bit bi-directional counters: -2,147,483,648 to +2,147,483,647. C200- 219 are general, C220- 234 are latched.
501
502 The counting direction is designated with special auxiliary relays M8200 to M8234. When the special auxiliary relay is ON, it is decremented; otherwise, it is counting up.
503
504 == **5.5.2 High speed counter** ==
505
506 Although counters C235 to C255 (21 points) are all high speed counters, they share the same range of high speed inputs. Therefore, if an input is already being used by a high speed counter, it couldnot be used for any other high speed counters or for any other purpose, i.e as an interrupt input.
507
508 The selection of high speed counters is not free, they are directly dependent on the type of counter required and which inputs are available.
509
510 * Available counter types
511
512 1. 1 phase with user start/reset: C235 to C240
513 1. 1 phase with assigned start/reset: C241 to C245
514 1. 2 phase bi-directional: C246 to C250
515 1. A/B phase type: C251 to C255
516
517 Different types of counters could be used at the same time but their inputs must not coin-cider. Inputs X0 to X7 couldnot be used for more than one counter.
518
519 Table 3
520
521 (% style="text-align:center" %)
522 [[image:1650088093463-330.png||class="img-thumbnail" height="209" width="1000"]]
523
524 U: up counter input
525
526 D: down counter input
527
528 R: reset counter (input)
529
530 S: start counter (input)
531
532 A: A phase counter input
533
534 B: B phase counter input
535
536 (((
537 === **5.5.2.1 1 phase** ===
538 )))
539
540 (% style="text-align:center" %)
541 [[image:1650088151106-380.png||class="img-thumbnail" height="192" width="300"]]
542
543 Figure 4
544
545 As above program shows, C244 is 1 phase high speed counter with start, stop and reset functions. From the table, X1~~X6 are for start and reset. C244 start counting when X12 and X6 are turned ON, the counter input terminal is X0, set value for C244 is determined by D0 (D1), so C244 could be reset by X0 or X11.
546
547 (((
548 === **5.5.2.2 2 phase** ===
549 )))
550
551 (% style="text-align:center" %)
552 [[image:1650088187166-773.png||class="img-thumbnail" height="208" width="500"]]
553
554 Figure 5
555
556 C251~~C255 are 2 phase (AB phase) high speed counter. As above (b) picture shows, C251 counts according from X0 (A phase) and X1 (B phase), when X14 is turned ON. C251 is reset when X13 is turned ON.
557
558 While A phase is turned ON, if B changes state from OFF to ON, C251 executes up count operation. While A phase is turn ON, if B changes state from ON to OFF, C251 executes down count operation. According to this principle, C251 executes up count operation while machine forward, and C251 executes down count operation while machine reverse. The M8251 monitors the C251's up / down counting status, OFF is for up counting, ON is for down counting.
559
560 === **5.5.2.3 Output Y: high speed pulse output transistor** ===
561
562 * It supports up to 4 channels, and each channel maximum output frequency is 200K;
563 * The output frequency could be used for controlling inverter, stepper and servo motors and so on;
564
565 === **5.5.2.4 Input X: one phase** ===
566
567 * X0, X1 hardware counters (C235, C236, C246), could support 200K pulse input at the same time;
568 * X0, X1 software counters (C241, C244, C247, C249), could support the input of 100K pulses at the same time;
569 * The hardware counter could be switched to software counting using HSCS, HSCR, HSZ instructions;
570 * The last four X points are software counting, which could support the input of 10K pulses at the same time.
571
572 === **5.5.2.5 Input X: A/B phase** ===
573
574 * X0, X1 hardware counter (C251), can support 100K pulse input;
575 * X0, X1 software counters (C252, C254) support the simultaneous input of 50K pulses at the same time;
576 * Hardware counter can be switched to software counter, using HSCS, HSCR, HSZ instructions;
577 * The remaining X points are counted by software, and each 5K pulse frequency can be input at the same time;
578 * There are two frequency modes for 2 phase 2 input, one is 2 times, and the other is 4 times, as following table shows, users select mode in D8200;
579
580 Table 6
581
582 (% class="table-bordered" %)
583 |**Value in D8200**|**Count icon**
584 |(((
585 K2
586
587 (two times)
588 )))|(((
589 (% style="text-align:center" %)
590 [[image:1650088281669-717.png||class="img-thumbnail" height="153" width="500"]]
591 )))
592 |(((
593 K4 or others
594
595 (four times)
596
597 (default)
598 )))|(((
599 (% style="text-align:center" %)
600 [[image:1650088272392-475.png||class="img-thumbnail" height="149" width="500"]]
601 )))
602
603 **✎Note: **
604 //**HSCS, HSCR and HSCZ couldn’t be used with Frequency multiplication**//
605
606 //**Program example1:**//
607
608 If X0 input pulse number >=800,The Y0 will set ON.
609
610 X6 means reset C235.
611
612 X7 means reset Y0.
613
614 You also could use M register instead of X registers.(M is a auxiliary register
615
616 **✎Note:** Wecon PLC X input need power DC24V signal.X0 and X1 support upto 200KHZ.X2~-~-~-~--X5 upto 10K.
617
618 (% style="text-align:center" %)
619 [[image:1650088411761-720.png||class="img-thumbnail" height="315" width="800"]]
620
621 //**Program example2: AB encoder**//
622
623
624 (% style="text-align:center" %)
625 [[image:1650088448077-686.png||class="img-thumbnail" height="137" width="850"]]
626
627
628 (% style="text-align:center" %)
629 [[image:1650088461137-192.png||class="img-thumbnail" height="333" width="700"]]
630
631 (% style="text-align:center" %)
632 [[image:1650088478181-407.png||class="img-thumbnail" height="683" width="850"]]
633
634 = **5.6 Register D** =
635
636 Data registers, as the name suggests, store data. The stored data could be interpreted as a numerical value or as a series of bits, being either ON or OFF. A single data register contains 16bits or one word. However, two consecutive data registers could be used to form a 32bit device more commonly known as a double word. If the contents of the data register are being considered numerically then the Most Significouldt Bit (MSB) is used to indicate if the data has a positive or negative bias. As bit devices could only be ON or OFF, 1 or 0 the MSB convention used is, 0 is equal to a positive number and 1 is equal to a negative number.
637
638 In WECON LX Series PLC, most data in the instructions are signed numbers. The bit 15 in 16-bit address is sign bit (0 means positive, 1 means negative). The high bit 15 in 32-bit address is sign bit, the data range is -32,768 - +32,767.
639
640 Devices numbered in: Decimal, i.e. D0 to D9, D10 to D19
641
642 (% class="table-bordered" %)
643 |=(% rowspan="2" style="width: 96px;" %)**PLC**|=(% rowspan="2" style="width: 108px;" %)**General**|=(% rowspan="2" style="width: 119px;" %)**Latched**|=(% colspan="2" style="width: 547px;" %)**Latched- specific**|=(% rowspan="2" %)**System- specific**|=(% rowspan="2" %)**Special**
644 |=(% style="width: 138px;" %)**-**|=**Files**
645 |(% style="width:96px" %)LX3V (1S firmware)|(% style="width:108px" %)(((
646 128 ※3
647
648 (D0-D127)
649 )))|(% style="width:119px" %)-|(% style="width:138px" %)(((
650 128 ※3
651
652 (D128-D255)
653 )))|D1000-D2499 could be used for files by parameter setting|(((
654 256
655
656 (D8000-D8255)
657 )))|(((
658 16
659
660 (V0-V7)
661
662 (Z0-Z7)
663 )))
664 |(% style="width:96px" %)LX3V (2N firmware)|(% style="width:108px" %)(((
665 200※1
666
667 (D0-D199)
668 )))|(% style="width:119px" %)(((
669 312※2
670
671 (D200-D511)
672 )))|(% style="width:138px" %)(((
673 7488 ※3
674
675 (D512-D7999)
676 )))|D1000-D7999 could be used for files by parameter setting|(((
677 256
678
679 (D8000-D8255)
680 )))|(((
681 16 ※3
682
683 (V0-V7)
684
685 (Z0-Z7)
686 )))
687 |(% style="width:96px" %)LX3VP|(% style="width:108px" %)(((
688 200※1
689
690 (D0-D199)
691 )))|(% style="width:119px" %)(((
692 312※2
693
694 (D200-D511)
695 )))|(% style="width:138px" %)(((
696 7488 ※3
697
698 (D512-D7999)
699 )))|D1000-D7999 could be used for files by parameter setting|(((
700 256
701
702 (D8000-D8255)
703 )))|(((
704 16 ※3
705
706 (V0-V7)
707
708 (Z0-Z7)
709 )))
710 |(% style="width:96px" %)LX3VE|(% style="width:108px" %)(((
711 200※1
712
713 (D0-D199)
714 )))|(% style="width:119px" %)(((
715 312※2
716
717 (D200-D511)
718 )))|(% style="width:138px" %)(((
719 7488 ※3
720
721 (D512-D7999)
722 )))|D1000-D7999 could be used for files by parameter setting|(((
723 256
724
725 (D8000-D8255)
726 )))|(((
727 16 ※3
728
729 (V0-V7)
730
731 (Z0-Z7)
732 )))
733 |(% style="width:96px" %)LX3VM|(% style="width:108px" %)(((
734 200※1
735
736 (D0-D199)
737 )))|(% style="width:119px" %)(((
738 312※2
739
740 (D200-D511)
741 )))|(% style="width:138px" %)(((
742 7488 ※3
743
744 (D512-D7999)
745 )))|D1000-D7999 could be used for files by parameter setting|(((
746 256
747
748 (D8000-D8255)
749 )))|(((
750 16 ※3
751
752 (V0-V7)
753
754 (Z0-Z7)
755 )))
756
757 ※1, Non-latched area, it could be changed to latched area by parameter setting.
758
759 ※2, Latched area, it could be changed to non-latched area by parameter setting.
760
761 ※3, The non-latched or latched feature couldnot be changed.
762
763 == **5.6.1 General** ==
764
765 A single data register contains 16bits or one word. However, two consecutive data registers could be used to form a 32bit device more commonly known as a double word. Data remains the same until the next time it is rewritten. When switch the PLC state (RUN to STOP or STOP to RUN), the data will be erased. If the special auxiliary relay M8033 is ON, the data in general data register will be retained while switch PLC state.
766
767 == **5.6.2 Latched** ==
768
769 The data in register will be retained while switch PLC state. The latched register range could be modified by parameters.
770
771 == **5.6.3 System-special** ==
772
773 System-special data register D8000 ~~ D8255 are used for controlling and monitoring a variety of work methods and components in PLC, such as battery voltage, scould time, and is the state of action and so on. The default value will be written into those registers while PLC power on.
774
775 == **5.6.4 Index registers V, Z** ==
776
777 The index registers are same as common data registers, is 16-bit registers for data reading and writing. There are totally 64 registers, V0-V31, Z0-Z31.
778
779 The index registers could be used in combination with other registers or values by application instructions. But they couldnot be used in combination with the basic instructions and step ladder diagram instruction.
780
781 == **5.6.5 File registers D** ==
782
783 The file registers start from D1000 to D7999. File registers could be secured in the program memory in units of 500 points. File registers are actually setup in the parameter area of the PLC. For every block of 500 file registers allocated and equivalent block of 500 program steps are lost.
784
785 = **5.7 Register P,I** =
786
787 Pointers register P is used for entry address of jump program, and identification of sub-program starting address.
788
789 Pointer register I is used for identification of interrupted program starting address.
790
791 Devices numbered in: Decimal, i.e. P0 to P9, P10 to P19, I0 to I9, I10 to I19.
792
793 (% class="table-bordered" %)
794 |=(% rowspan="2" %)**PLC**|=(% colspan="2" style="width: 255px;" %)**Sub-program**|=(% rowspan="2" style="width: 404px;" %)**Insert**|=(% rowspan="2" %)**Insert counter**|=(% rowspan="2" %)**Counter interrupt**
795 |(% style="width:126px" %)**-**|(% style="width:129px" %)**Jump to end**
796 |LX3V (1S)|(% style="width:126px" %)(((
797 63
798
799 (P0-P62)
800 )))|(% style="width:129px" %)(((
801 1
802
803 (P63)
804 )))|(% style="width:404px" %)(((
805 6
806
807 I00_(X000), I10_(X001), I20_(X002), I30_(X003), I40_(X004), I50_(X005)
808 )))|-|-
809 |LX3V (2N)|(% style="width:126px" %)(((
810 127
811
812 (P0-P62)
813
814 (P64-P127)
815 )))|(% style="width:129px" %)(((
816 1
817
818 (P63)
819 )))|(% style="width:404px" %)(((
820 6
821
822 I00_(X000), I10_(X001), I20_(X002), I30_(X003), I40_(X004), I50_(X005)
823 )))|(((
824 3
825
826 (I6_, I7_, I8_)
827 )))|(((
828 6
829
830 (I010, I020, I030, I040, I050, I060)
831 )))
832 |LX3VP|(% style="width:126px" %)(((
833 127
834
835 (P0-P62)
836
837 (P64-P127)
838 )))|(% style="width:129px" %)(((
839 1
840
841 (P63)
842 )))|(% style="width:404px" %)(((
843 6
844
845 I00_(X000), I10_(X001), I20_(X002), I30_(X003), I40_(X004), I50_(X005)
846 )))|(((
847 3
848
849 (I6_, I7_, I8_)
850 )))|(((
851 6
852
853 (I010, I020, I030, I040, I050, I060)
854 )))
855 |LX3VE|(% style="width:126px" %)(((
856 127
857
858 (P0-P62)
859
860 (P64-P127)
861 )))|(% style="width:129px" %)(((
862 1
863
864 (P63)
865 )))|(% style="width:404px" %)(((
866 6
867
868 I00_(X000), I10_(X001), I20_(X002), I30_(X003), I40_(X004), I50_(X005)
869 )))|(((
870 3
871
872 (I6_, I7_, I8_)
873 )))|(((
874 6
875
876 (I010, I020, I030, I040, I050, I060)
877 )))
878 |LX3VM|(% style="width:126px" %)(((
879 127
880
881 (P0-P62)
882
883 (P64-P127)
884 )))|(% style="width:129px" %)(((
885 1
886
887 (P63)
888 )))|(% style="width:404px" %)(((
889 6
890
891 I00_(X000), I10_(X001), I20_(X002), I30_(X003), I40_(X004), I50_(X005)
892 )))|(((
893 3
894
895 (I6_, I7_, I8_)
896 )))|(((
897 6
898
899 (I010, I020, I030, I040, I050, I060)
900 )))
901
902 **✎Note: **
903
904 The input X for interrupt register couldn’t be used for [high speed counter] and [SPD] instruction as the same time.
905
906 1. Sub-program pointer
907
908 As below demos show, the left one is for conditional jump with [CJ] instruction, the right one is for Sub-program call with [CALL] instruction.
909
910 (% style="text-align:center" %)
911 [[image:1650093462249-520.png||class="img-thumbnail" height="399" width="700"]]
912
913 == **5.7.1 Interrupt pointer** ==
914
915 An interrupt pointer and various usage of three, dedicated interrupt applied instructions;
916
917 * IRET: interrupt return
918 * EI: enable interrupt
919 * DI: disable interrupt
920
921 == **5.7.2 Usage of interrupt** ==
922
923 * Input Interrupt: Receive signals from a particular input without being affected by the scould cycle of PLC;
924 * Timer Interrupt: The interrupt is repeatedly triggered at intervals of the specified time (10ms~~99ms);
925 * Counter Interrupt: The interrupt is triggered according to the comparison result of the built-in high-speed counter of PLC;
926
927 LX Series PLC could support five kinds of contacts for programming, the detailed as the following table shows.
928
929 (% class="table-bordered" %)
930 |**Format**|**Description**
931 |Decimal|(((
932 The set value of timer and counter (K is a constant);
933
934 The number of Auxiliary Relay(M), Timer(T), Counter(C), Status(S) and so on (the number of registers);
935
936 The value and instruction action in the operand, which are applied (K is a constant);
937 )))
938 |Hexadecimal|As with the decimal, it is applied in the operand and the specific actions in the application instruction.
939 |Binary|Using decimal number or hexadecimal number to design the value of the timer, counter or data register. However, in the internal PLC, these data is dealt with binary numbers. Moreover, when monitoring external devices, these registers will be converted to a decimal number automatically (16 hex could be converted as well).
940 |Octal|It is used for distribute the register number of input relay and output relay. Use the binary values of [0-7, 10-17 ... 70-77, 100-107]. [8, 9] do not exist in the octal.
941 |BCD|Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four or eight. Special bit patterns are sometimes used forseven segment display controlling.
942 |BIN float|BIN float is used for calculation in PLC internal.
943 |Decimal float|It is only used for monitoring and improving readability.
944
945 = **5.8.1 Constant K** =
946
947 [K] is decimal integer symbol, mainly used for setting the value of the timer or counter or application instruction operand values. The value range in 16-bit is -32,768 – 32,767, the value range in 32-bit is -2, 147,483, 648 – 2, 147, 483, 647.
948
949 = **5.8.2 Constant H** =
950
951 [H] is hexadecimal numbers symbol, mainly used for setting the value of application instruction operand value. The value range in 16-bit instruction is 0000-FFFF, the value range in 32-bit instruction is 0000, 0000– FFFF, FFFF.
952
953 = **5.8.3 Constant E** =
954
955 [E] is single-precision floating symbol, mainly used for setting the value of application instruction operand value. It is only available in DECMP、DEZCP、DSINH、DCOSH、DTANH、DEBCD、DEBIN、DEADD、DESUB、DEMUL、DEDIV、DEXP、DLOGE、DLOG10、DESQR、DINT、DSIN、DCOS、DTAN、DASIN、DACOS、 DATAN、DRAD、DDEG instructions in LX3VP and LX3VE series. The value range is ±1.175495 E-38～±3.402823 E+38.
956
957 (% style="text-align:center" %)
958 [[image:1650093586748-193.png||class="img-thumbnail" height="62" width="500"]]
959
960 = **5.9 System-special address** =
961
962 (% class="table-bordered" %)
963 |=**M**|=(% colspan="2" %)**Description**|=**LX1S**|=**LX2N or later**|=**D**|=(% colspan="3" %)**Description**|=**LX1S**|=**LX2N or later**|=
964 |(% colspan="11" %)(((
965 == **5.9.1 System operation** ==
966 )))|
967
968 (% class="table-bordered" %)
969 |=M8000|=(% colspan="2" %)RUN monitor, NO contact|=O|=O|=D8000|=(% colspan="3" %)Watchdog timer|=O|=O|=
970 |M8001|(% colspan="2" %)RUN monitor, NC contact|O|O|D8001|(% colspan="3" %)(((
971 PLC type and version
972
973 LX3V/3V-A2:250~*~*
974
975 LX3V-A1: 220~*~*
976
977 LX3VP: 251~*~*
978
979 LX2V: 240~*~*
980
981 ~** is viewed by D8101
982 )))|O|O|
983 |M8002|(% colspan="2" %)Initial pulse NO contact|O|O|D8002|(% colspan="3" %)(((
984 Memory capacity
985
986 0002: 2K steps
987
988 0004: 4K steps
989
990 0008: 8K step
991 )))|O|O|
992 |M8003|(% colspan="2" %)Initial pulse NC contact|O|O|D8003|(% colspan="3" %)Memory type default value is 0x10.|O|O|
993 |M8004|(% colspan="2" %)ON when one or more error flags from the range M8060to M8067 [except M8062]are ON|O|O|D8004|(% colspan="3" %)Error BCD code of M8060~~M8067, the default value is 0.|O|O|
994 |M8005|(% colspan="2" %)Battery voltage Low|-|O|D8005|(% colspan="3" %)Battery voltage|-|O|
995 |M8006|(% colspan="2" %)Battery error latch|-|O|D8006|(% colspan="3" %)The level at which a battery voltage low is detected|-|O|
996 |M8007|(% colspan="2" %)Power loss has occurred more than 5ms, M8007&M8008 are ON|-|O|D8007|(% colspan="3" %)The number of time a momentary power failure has occurred since power ON.|-|O|
997 |M8008|(% colspan="2" %)Power loss has occurred|-|O|D8008|(% colspan="3" %)The time period before shutdown when a power failure occurs (default 10ms)|-|O|
998 |M8009|(% colspan="2" %)Power failure of 24V DC service supply|-|O|D8009|(% colspan="3" %)The device number of module, which affected by 24VDC power failure|-|O|
999 |(% colspan="11" %)(((
1000 == **5.9.2 Clock Devices** ==
1001 )))|
1002 |M8010|(% colspan="2" %)Reserved|O|O|D8010|(% colspan="3" %)Current operation cycle / scould time in units of 0.1 msec|O|O|
1003 |M8011|(% colspan="2" %)Oscillates in 10 msec cycles|O|O|D8011|(% colspan="3" %)Minimum cycle/ scould time in units of 0.1 msec|O|O|
1004 |M8012|(% colspan="2" %)(((
1005 Oscillates in 100 msec
1006
1007 cycles
1008 )))|O|O|D8012|(% colspan="3" %)Maximum cycle/ scould time inunits of 0.1 msec|O|O|
1009 |M8013|(% colspan="2" %)Oscillates in 1 sec cycles|O|O|D8013|(% colspan="3" %)Seconds data for use with an RTC (0-59)|O|O|
1010 |M8014|(% colspan="2" %)Oscillates in 1 min cycles|O|O|D8014|(% colspan="3" %)Minute data for use with anRTC (0-59)|O|O|
1011 |M8015|(% colspan="2" %)When ON - clock stops, ON→OFF restarts clock|O|O|D8015|(% colspan="3" %)Hour data for use with an RTC (0-23)|O|O|
1012 |M8016|(% colspan="2" %)(((
1013 When ON D8013 to 19 are frozen for display but clock
1014
1015 continues
1016 )))|O|O|D8016|(% colspan="3" %)Day data for use with an RTC (1-31)|O|O|
1017 |M8017|(% colspan="2" %)When pulsed ON set RTC to nearest minute|O|O|D8017|(% colspan="3" %)Month data for use with an RTC (1-12)|O|O|
1018 |M8018|(% colspan="2" %)When ON Real Time Clockis installed|O|O|D8018|(% colspan="3" %)Year data for use with an RTC (2000-2099)|O|O|
1019 |M8019|(% colspan="2" %)Clock data has been set outof range|O|O|D8019|(% colspan="3" %)Weekday data for use with an RTC (0-6)|O|O|
1020 |(% colspan="11" %)(((
1021 == **5.9.3 Operation Flags** ==
1022 )))|
1023 |M8020|(% colspan="2" %)Set when the result of anADDor SUBis “0”|O|O|D8020|(% colspan="3" %)Input filter setting for devicesX000 to X007 default is 10msec, (0-60)|O|O|
1024 |M8021|(% colspan="2" %)(((
1025 Set when the result of a SUBis less than the
1026
1027 min. negative number
1028 )))|O|O|D8021|(% colspan="3" %)Reserved| | |
1029 |M8022|(% colspan="2" %)Set when ‘carry’ occurs during an ADD orwhen an overflow occurs asa result of a data shift operation|O|O|D8022|(% colspan="3" %)Reserved| | |
1030 |M8023|(% colspan="2" %)Reserved|O|O|D8023|(% colspan="3" %)Reserved| | |
1031 |M8024|(% colspan="2" %)Direction of BMOV|-|O|D8024|(% colspan="3" %)Reserved| | |
1032 |M8025|(% colspan="2" %)HSC mode|-|O|D8025|(% colspan="3" %)Reserved| | |
1033 |M8026|(% colspan="2" %)RAMP mode|-|O|D8026|(% colspan="3" %)Reserved| | |
1034 |M8027|(% colspan="2" %)PR 16 element data string|-|O|D8027|(% colspan="3" %)Reserved| | |
1035 |M8028|(% colspan="2" %)Switch100ms/10ms timer|O|-|D8028|(% colspan="3" %)Current value of the Z index register|O|O|
1036 |M8029|(% colspan="2" %)Instruction execution complete such as PLSR|O|O|D8029|(% colspan="3" %)Current value of the V index register|O|O|
1037 |(% colspan="11" %)(((
1038 == **5.9.4 PLC Operation Mode** ==
1039 )))|
1040 |M8030|(% colspan="2" %)Battery voltage is low but BATT.V LED not lit|-|O|D8030|(% colspan="3" %)Reserved| | |
1041 |M8031|(% colspan="2" %)Clear all unsaved memory|O|O|D8031|(% colspan="3" %)Reserved| | |
1042 |M8032|(% colspan="2" %)Clear all the saved memory|O|O|D8032|(% colspan="3" %)Reserved| | |
1043 |M8033|(% colspan="2" %)The device statuses and settings are retained when thePLC changes from RUN toSTOP and back into RUN|O|O|D8033|(% colspan="3" %)Reserved| | |
1044 |M8034|(% colspan="2" %)All of the physical switchgear for activating outputs is disabled. However, the program still operates normally.|O|O|D8034|(% colspan="3" %)Reserved| | |
1045 |M8035|(% colspan="2" %)Forced operation 1|O|O|D8035|(% colspan="3" %)Reserved| | |
1046 |M8036|(% colspan="2" %)Forced operation 2|O|O|D8036|(% colspan="3" %)Reserved| | |
1047 |M8037|(% colspan="2" %)Forced stop|O|O|D8037|(% colspan="3" %)Reserved| | |
1048 |M8038|(% colspan="2" %)Communication parameter setting flag|O|O|D8038|(% colspan="3" %)Reserved| | |
1049 |M8039|(% colspan="2" %)Constant scould|O|O|D8039|(% colspan="3" %)Constant scould time, default 0, in units of MS|O|O|
1050 |(% colspan="11" %)(((
1051 == **5.9.5 Step Ladder (STL) Flags** ==
1052 )))|
1053 |M8040|(% colspan="2" %)When ON STL state transfer is disabled|O|O|D8040|(% colspan="3" rowspan="8" %)Up to 8 active STL states, from the range S0 to S899, are stored in D8040 to D8047 in ascending numerical order (Updated at END)|O|O|
1054 |M8041|(% colspan="2" %)When ON STL transfer from initial state is enabled during automatic operation|O|O|D8041|O|O|
1055 |M8042|(% colspan="2" %)A pulse output is given in response to a start input|O|O|D8042|O|O|
1056 |M8043|(% colspan="2" %)On during the last state of ZERO RETURN mode|O|O|D8043|O|O|
1057 |M8044|(% colspan="2" %)ON when the machine zero is detected|O|O|D8044|O|O|
1058 |M8045|(% colspan="2" %)Disables the all output reset function when the operation mode is changed|O|O|D8045|O|O|
1059 |M8046|(% colspan="2" %)ON when STL monitoring has been enable (M8047)|O|O|D8046|O|O|
1060 |M8047|(% colspan="2" %)When ON D8040 to D8047 are enabled for active STL step monitoring|O|O|D8047|O|O|
1061 |M8048|(% colspan="2" %)ON when annunciator monitoring has been enabled (M8049) and there is an active annunciator flag|-|O|D8048|(% colspan="3" %)Reserved| | |
1062 |M8049|(% colspan="2" %)When ON D8049 is enabled for actove annunciator state monitoring.|-|O|D8049|(% colspan="3" %)Stores the lowest currently active annunciator from the range S900 to S999 (Updated at END)|-|O|
1063 |(% colspan="11" %)(((
1064 == **5.9.6 Interrupt Control Flags** ==
1065 )))|
1066 |M8050|(% colspan="2" %)I00□ disabled|O|O|D8050|(% colspan="3" %)Reserved| | |
1067 |M8051|(% colspan="2" %)I10□ disabled|O|O|D8051|(% colspan="3" %)Reserved| | |
1068 |M8052|(% colspan="2" %)I20□ disabled|O|O|D8052|(% colspan="3" %)Reserved| | |
1069 |M8053|(% colspan="2" %)I30□ disabled|O|O|D8053|(% colspan="3" %)Reserved| | |
1070 |M8054|(% colspan="2" %)I40□ disabled|O|O|D8054|(% colspan="3" %)Reserved| | |
1071 |M8055|(% colspan="2" %)I50□ disabled|O|O|D8055|(% colspan="3" %)Reserved| | |
1072 |M8056|(% colspan="2" %)I6□□ disabled|-|O|D8056|(% colspan="3" %)Reserved| | |
1073 |M8057|(% colspan="2" %)I7□□ disabled|-|O|D8057|(% colspan="3" %)Reserved| | |
1074 |M8058|(% colspan="2" %)I8□□ disabled|-|O|D8058|(% colspan="3" %)Reserved| | |
1075 |M8059|(% colspan="2" %)Counters disabled|-|O|D8059|(% colspan="3" %)Reserved| | |
1076 |(% colspan="11" %)(((
1077 == **5.9.7 Error Detection** ==
1078 )))|
1079 |M8060|(% colspan="2" %)I/O configuration error|-|O|D8060|(% colspan="3" %)The first I/O number of the unit or block causing the error|-|O|
1080 |M8061|(% colspan="2" %)PLC hardware error|O|O|D8061|(% colspan="3" %)Error code for hardware error|O|O|
1081 |M8062|(% colspan="2" %)PLC communication error|-|O|D8062|(% colspan="3" %)Error code for PLC Communications error|-|O|
1082 |M8063|(% colspan="2" %)Parallel link error|O|O|D8063|(% colspan="3" %)Error code for parallel link error|O|O|
1083 |M8064|(% colspan="2" %)Parameter error|O|O|D8064|(% colspan="3" %)Error code identifying parameter error|O|O|
1084 |M8065|(% colspan="2" %)Syntax error|O|O|D8065|(% colspan="3" %)Error code identifying syntax error|O|O|
1085 |M8066|(% colspan="2" %)Loop error|O|O|D8066|(% colspan="3" %)Error code identifying loop error|O|O|
1086 |M8067|(% colspan="2" %)Operation error|O|O|D8067|(% colspan="3" %)Error code identifying operation error.|O|O|
1087 |M8068|(% colspan="2" %)Operation error latch|O|O|D8068|(% colspan="3" %)Operation error step number latched|O|O|
1088 |M8069|(% colspan="2" %)Reserved| | |D8069|(% colspan="3" %)Step numbers for found errors corresponding to flags M8065 to M8067|O|O|
1089 |(% colspan="11" %)(((
1090 == **5.9.8 High-speed ring counter** ==
1091 )))|
1092 |M8099|(% colspan="2" %)High-speed ring counter operation|O|O|D8099|(% colspan="3" %)High-speed ring counter, range: 0 to 32,767 in units of 0.1 ms|O|O|
1093 |(% colspan="11" %)(((
1094 == **5.9.9 Other functions** ==
1095 )))|
1096 |M8100|(% colspan="2" %)SPD (X000) pulse/ minute|O|O|D8100|(% colspan="3" %)Reserved|O|O|
1097 |M8101|(% colspan="2" %)SPD (X001) pulse/ minute|O|O|D8101|(% colspan="3" %)(((
1098 Firmware sub-version
1099
1100 LX3V/3VP: 160~*~*
1101
1102 LX2V: 240~*~*
1103
1104 The ~*~* and D8001~*~* combines a complete firmware version number
1105 )))|O|O|
1106 |M8102|(% colspan="2" %)SPD (X002) pulse/ minute|O|O|D8102|(% colspan="3" %)User program capacity|O|O|
1107 |M8103|(% colspan="2" %)SPD (X003) pulse/ minute|O|O|D8103|(% colspan="3" %)Reserved|O|O|
1108 |M8104|(% colspan="2" %)SPD (X004) pulse/ minute|O|O|D8104|(% colspan="3" %)The AC/DE time for DRVI, DRVA, [100 ms default value] it effected by M8135 (Y0), it must be the same as D8165.|O|O|
1109 |M8105|(% colspan="2" %)SPD (X005) pulse/ minute|O|O|D8105|(% colspan="3" %)The AC/DE time for DRVI, DRVA, [100 ms default value] it effected by M8135 (Y1), it must be the same as D8166.|O|O|
1110 |M8106|(% colspan="2" %)Reserved| | |D8106|(% colspan="3" %)The AC/DE time for DRVI, DRVA, [100 ms default value] it effected by M8135 (Y2), it must be the same as D8167.|O|O|
1111 |M8107|(% colspan="2" %)Reserved| | |D8107|(% colspan="3" %)The AC/DE time for DRVI, DRVA, [100 ms default value] it effected by M8135 (Y3), it must be the same as D8168.|O|O|
1112 |M8108|(% colspan="2" %)Reserved| | |D8108|(% colspan="3" %)Reserved| | |
1113 |M8109|(% colspan="2" %)Output refresh error|O|O|D8109|(% colspan="3" %)Output refresh error device number;|O|O|
1114 |(% colspan="11" %)(((
1115 == **5.9.10 COM1 communication settings** ==
1116 )))|
1117 |M8110|(% colspan="2" %)Reserved| | |D8110|(% colspan="3" %)Com1 port setting (only available in 22319, 24320, 25007 or later)|O|O|
1118 |M8111|(% colspan="2" %)Reserved| | |D8111|(% colspan="3" %)Reserved| | |
1119 |M8112|(% colspan="2" %)BD module 1 channel 1 flag bit| | |D8112|(% colspan="3" %)BD module 1 channel 1 data| | |
1120 |M8113|(% colspan="2" %)BD module 1 channel 2 flag bit| | |D8113|(% colspan="3" %)BD module 1 channel 2 data| | |
1121 |M8114|(% colspan="2" %)BD module 1 channel 3 flag bit| | |D8114|(% colspan="3" %)BD module 1 channel 3 data| | |
1122 |M8115|(% colspan="2" %)BD module 1 channel 4 flag bit| | |D8115|(% colspan="3" %)BD module 1 channel 4 data| | |
1123 |M8116|(% colspan="2" %)BD module 2 channel 1 flag bit| | |D8116|(% colspan="3" %)BD module 2 channel 1 data| | |
1124 |M8117|(% colspan="2" %)BD module 2 channel 2 flag bit| | |D8117|(% colspan="3" %)BD module 2 channel 2 data| | |
1125 |M8118|(% colspan="2" %)BD module 2 channel 3 flag bit| | |D8118|(% colspan="3" %)BD module 2 channel 3 data| | |
1126 |M8119|(% colspan="2" %)BD module 2 channel 4 flag bit| | |D8119|(% colspan="3" %)BD module 2 channel 4 data| | |
1127 |(% colspan="11" %)(((
1128 == **5.9.11 COM2 communication settings** ==
1129 )))|
1130 |M8120|(% colspan="2" %)Reserved| | |D8120|(% colspan="3" %)Com2 port setting, the default value is 0|O|O|
1131 |M8121|(% colspan="2" %)Sending and waiting (RS instruction)|O|O|D8121|(% colspan="3" %)Station number settings, the default value is 1|O|O|
1132 |M8122|(% colspan="2" %)(((
1133 Sending flag (RS instruction)
1134
1135 Instruction execution status (MODBUS)
1136 )))|O|O|D8122|(% colspan="3" %)Amount of remaining data to be transmitted (Only for RS instruction) unit:0.1ms|O|O|
1137 |M8123|(% colspan="2" %)(((
1138 Receiving complete flag (RS)
1139
1140 Communication error flag (MODBUS)
1141 )))|O|O|D8123|(% colspan="3" %)Amount of data already received (Only to RS instruction)|O|O|
1142 |M8124|(% colspan="2" %)Receiving (only to RS instruction)|O|O|D8124|(% colspan="3" %)Start character STX (Only to RS instruction)|O|O|
1143 |M8125|(% colspan="2" %)Reserved| | |D8125|(% colspan="3" %)End character ETX (Only to RS instruction)|O|O|
1144 |M8126|(% colspan="2" %)Reserved| | |D8126|(% colspan="3" %)Communication protocol setting, the default value is 0|O|O|
1145 |M8127|(% colspan="2" %)Reserved| | |D8127|(% colspan="3" %)Starting address for PC protocol|O|O|
1146 |M8128|(% colspan="2" %)Reserved| | |D8128|(% colspan="3" %)Data length for PC protocol|O|O|
1147 |M8129|(% colspan="2" %)Timeout judgement|O|O|D8129|(% colspan="3" %)Timeout judgement, default value is 10 (100ms)|O|O|
1148 |(% colspan="11" %)(((
1149 == **5.9.12 High speed & Position** ==
1150 )))|
1151 |M8130|(% colspan="2" rowspan="2" %)Selects comparison tables to be used with the HSZ instruction|O|O|D8130|(% colspan="3" %)Contains the number of the current record being processed in the HSZ comparison table|O|O|
1152 |M8131|O|O|D8131|(% colspan="3" %)HSZ&PLSY speed mode|O|O|
1153 |M8132|(% colspan="2" rowspan="2" %)HSZ&PLSY speed mode|O|O|D8132|(% rowspan="2" %)HSZ&PLAY speed mode frequency|(% colspan="2" %)Low|(% rowspan="2" %)O|(% rowspan="2" %)O|
1154 |M8133|O|O|D8133|(% colspan="2" %)-|
1155 |M8134|(% colspan="2" %)Reserved| | |D8134|(% rowspan="2" %)HSZ&PLAY speed mode pulses|(% colspan="2" %)Low|(% rowspan="2" %)O|(% rowspan="2" %)O|
1156 |M8135|(% colspan="2" %)Reserved| | |D8135|(% colspan="2" %)High|
1157 |M8136|(% colspan="2" %)Reserved| | |D8136|(% rowspan="2" %)total output pulse of Y000&Y001|(% colspan="2" %)Low|(% rowspan="2" %)O|(% rowspan="2" %)O|
1158 |M8137|(% colspan="2" %)Reserved| | |D8137|(% colspan="2" %)High|
1159 |M8138|(% colspan="2" %)Reserved| | |D8138|(% colspan="3" %)Reserved| | |
1160 |M8139|(% colspan="2" %)Reserved| | |D8139|(% colspan="3" %)Reserved| | |
1161 |M8140|(% colspan="2" %)The CLR signal output function of ZRN is valid|O|O|D8140|(% rowspan="2" %)Accumulated value of PLSY & PLSR output pulse in Y000|(% colspan="2" %)Low|(% rowspan="2" %)O|(% rowspan="2" %)O|
1162 |M8141|(% colspan="2" %)Accumulator register of output pulse could latched when turn ON (D8136, D8137, D8140~~D8143, D8150~~D8153)|O|O|D8141|(% colspan="2" %)High|
1163 |M8142|(% colspan="2" %)Reserved| | |D8142|(% rowspan="2" %)Accumulated value of PLSY & PLSR output pulse in Y001|(% colspan="2" %)Low|(% rowspan="2" %)O|(% rowspan="2" %)O|
1164 |M8143|(% colspan="2" %)Reserved| | |D8143|(% colspan="2" %)High|
1165 |M8144|(% colspan="2" %)Reserved| | |D8144|(% colspan="3" %)Reserved| | |
1166 |M8145|(% colspan="2" %)Stop pulse output in Y000|O|O|D8145|(% colspan="3" %)Bias speed of DRVI & DRVA|O|O|
1167 |M8146|(% colspan="2" %)Stop pulse output in Y001|O|O|D8146|(% rowspan="2" %)Highest speed of DRVI & DRVA (default is 100,000)|(% colspan="2" %)Low|(% rowspan="2" %)O|(% rowspan="2" %)O|
1168 |M8147|(% colspan="2" %)Monitor pulse output in Y000|O|O|D8147|(% colspan="2" %)High|
1169 |M8148|(% colspan="2" %)Monitor pulse output in Y001|O|O|D8148|(% colspan="3" %)ACC/DEC time of DRVI & DRVA (default is 100)|O|O|
1170 |M8149|(% colspan="2" %)Monitor pulse output in Y002|O|O|D8149|(% colspan="3" %)Reserved| | |
1171 |M8150|(% colspan="2" %)Monitor pulse output in Y003|O|O|D8150|(% colspan="2" rowspan="2" %)Accumulated value of PLSY & PLSR output pulse in Y002|Low|(% rowspan="2" %)O|(% colspan="2" rowspan="2" %)O
1172 |M8151|(% colspan="2" %)Reserved| | |D8151|High
1173 |M8152|(% colspan="2" %)Stop pulse output in Y002|O|O|D8152|(% colspan="2" rowspan="2" %)Accumulated value of PLSY & PLSR output pulse in Y003|Low|(% rowspan="2" %)O|(% colspan="2" rowspan="2" %)O
1174 |M8153|(% colspan="2" %)Stop pulse output in Y003|O|O|D8153|High
1175 |M8154|(% colspan="2" %)Reserved| | |D8154|(% colspan="3" %)Reserved| | |
1176 |M8155|(% colspan="2" %)Reserved| | |D8155|(% colspan="3" %)Reserved| | |
1177 |(% colspan="11" %)(((
1178 == **5.9.13 Extend function** ==
1179 )))|
1180 |M8156|(% colspan="2" %)Reserved| | |D8156|(% colspan="3" %)Define clear signal in Y0 (ZRN) (default is 5=Y5)|O|O|
1181 |M8157|(% colspan="2" %)Reserved| | |D8157|(% colspan="3" %)Define clear signal in Y1 (ZRN) (default is 6=Y6)|O|O|
1182 |M8158|(% colspan="2" %)Reserved| | |D8158|(% colspan="3" %)Define clear signal in Y2 (ZRN) (default is 7=Y7)|O|O|
1183 |M8159|(% colspan="2" %)Reserved| | |D8159|(% colspan="3" %)Define clear signal in Y3 (ZRN) (default is 8=Y10)|O|O|
1184 |M8160|(% colspan="2" %)SWAP function is XCH|-|O|D8160|(% colspan="3" %)Define clear signal in Y4 (ZRN) (default is 9=Y11)|O|O|
1185 |M8161|(% colspan="2" %)Bit processing mode of ASC/RS/ASCII/HEX/CCD|O|O|D8161|(% colspan="3" %)Reserved| | |
1186 |M8162|(% colspan="2" %)High-speed connection in parallel mode|O|O|D8162|(% colspan="3" %)Reserved| | |
1187 |M8163|(% colspan="2" %)Reserved| | |D8163|(% colspan="3" %)Reserved| | |
1188 |M8164|(% colspan="2" %)Variable transmission points mode (FROM/TO)|-|O|D8164|(% colspan="3" %)Special transmission points mode (FROM/TO)|O|O|
1189 |M8165|(% colspan="2" %)Reserved| | |D8165|(% colspan="3" %)When enable acceleration and deceleration time, ensure the values is the same as D8104's|O|O|
1190 |M8166|(% colspan="2" %)Reserved| | |D8166|(% colspan="3" %)When enable acceleration and deceleration time, ensure the values is the same as D8105's|O|O|
1191 |M8167|(% colspan="2" %)HEX processing function of SMOV|-|O|D8167|(% colspan="3" %)When enable acceleration and deceleration time, ensure the values is the same as D8106's|O|O|
1192 |M8168|(% colspan="2" %)HEX processing function of HEY|-|O|D8168|(% colspan="3" %)When enable acceleration and deceleration time, ensure the values is the same as D8107's|O|O|
1193 |M8169|(% colspan="2" %)Reserved| | |D8169|(% colspan="3" %)Reserved| | |
1194 |(% colspan="5" %)**Pulse catch**|(% colspan="6" %)**Communication**|
1195 |M8170|(% colspan="2" %)X000 pulse catch|O|O|D8170|(% colspan="3" %)Reserved| | |
1196 |M8171|(% colspan="2" %)X001 pulse catch|O|O|D8171|(% colspan="3" %)Reserved| | |
1197 |M8172|(% colspan="2" %)X002 pulse catch|O|O|D8172|(% colspan="3" %)Reserved| | |
1198 |M8173|(% colspan="2" %)X003 pulse catch|O|O|D8173|(% colspan="3" %)Station number setting state|O|O|
1199 |M8174|(% colspan="2" %)X004 pulse catch|O|O|D8174|(% colspan="3" %)Communication sub-station setting state|O|O|
1200 |M8175|(% colspan="2" %)X005 pulse catch|O|O|D8175|(% colspan="3" %)Refresh range setting state|O|O|
1201 |M8176|(% colspan="2" %)Reserved| | |D8176|(% colspan="3" %)Station number setting|O|O|
1202 |M8177|(% colspan="2" %)Reserved| | |D8177|(% colspan="3" %)Communication sub-station setting|O|O|
1203 |M8178|(% colspan="2" %)Reserved| | |D8178|(% colspan="3" %)Refresh range setting|O|O|
1204 |M8179|(% colspan="2" %)Reserved| | |D8179|(% colspan="3" %)Retries setting|O|O|
1205 |M8180|(% colspan="2" %)Reserved| | |D8180|(% colspan="3" %)Timeout setting|O|O|
1206 |(% colspan="5" %)**Communication**|(% colspan="6" %)**Indexed addressing**|
1207 |M8181|(% colspan="2" %)Reserved| | |D8181|(% colspan="3" %)Reserved| | |
1208 |M8182|(% colspan="2" %)Reserved| | |D8182|(% colspan="3" %)No.2 bit device/ Content of Z1 device|O|O|
1209 |M8183|(% colspan="2" %)Master transfers data error|O|O|D8183|(% colspan="3" %)No.3 bit device/ Content of V1 device|O|O|
1210 |M8184|(% colspan="2" %)Slave 1 transfers data error|O|O|D8184|(% colspan="3" %)No.4 bit device/ Content of Z2 device|O|O|
1211 |M8185|(% colspan="2" %)Slave 2 transfers data error|O|O|D8185|(% colspan="3" %)No.5 bit device/ Content of V2 device|O|O|
1212 |M8186|(% colspan="2" %)Slave 3 transfers data error|O|O|D8186|(% colspan="3" %)No.6 bit device/ Content of Z3 device|O|O|
1213 |M8187|(% colspan="2" %)Slave 4 transfers data error|O|O|D8187|(% colspan="3" %)No.7 bit device/ Content of V3 device|O|O|
1214 |M8188|(% colspan="2" %)Slave 5 transfers data error|O|O|D8188|(% colspan="3" %)No.8 bit device/ Content of Z4 device|O|O|
1215 |M8189|(% colspan="2" %)Slave 6 transfers data error|O|O|D8189|(% colspan="3" %)No.9 bit device/ Content of V4 device|O|O|
1216 |M8190|(% colspan="2" %)Slave 7 transfers data error|O|O|D8190|(% colspan="3" %)No.10 bit device/ Content of Z5 device|O|O|
1217 |M8191|(% colspan="2" %)Data transferring|O|O|D8191|(% colspan="3" %)No.11 bit device/ Content of V5 device|O|O|
1218 |M8192|(% colspan="2" %)Reserved| | |D8192|(% colspan="3" %)No.12 bit device/ Content of Z6 device|O|O|
1219 |M8193|(% colspan="2" %)Reserved| | |D8193|(% colspan="3" %)No.13 bit device/ Content of V6 device|O|O|
1220 |M8194|(% colspan="2" %)Reserved| | |D8194|(% colspan="3" %)No.14 bit device/ Content of Z7 device|O|O|
1221 |M8195|(% colspan="2" %)Reserved| | |D8195|(% colspan="3" %)No.15 bit device/ Content of V7 device|O|O|
1222 |M8196|(% colspan="2" %)Reserved| | |D8196|(% colspan="3" %)Reserved| | |
1223 |M8197|(% colspan="2" %)Reserved| | |D8197|(% colspan="3" %)Reserved| | |
1224 |M8198|(% colspan="2" %)Reserved| | |D8198|(% colspan="3" %)Reserved| | |
1225 |M8199|(% colspan="2" %)Reserved| | |D8199|(% colspan="3" %)Reserved| | |
1226 |(% colspan="5" %)**Counters states**|(% colspan="6" %)**Communication**|
1227 |M8200|(% colspan="2" %)C200 Control|O|O|D8200|(% colspan="3" %)(((
1228 Frequency multiplication of C251 device
1229
1230 D8200=0: 1 frequency multiplication
1231
1232 D8200=1: 2 frequency multiplication
1233
1234 D8200=2: 4 frequency multiplication
1235
1236 Note: HSCS, HSCR and HSCZ instructions could be used with frequency multiplication simultaneously. And this function is available in V311 or later version
1237 )))|O|O|
1238 |M8201|(% colspan="2" %)C201 Control|O|O|D8201|(% colspan="3" %)Reserved| | |
1239 |M8202|(% colspan="2" %)C202 Control|O|O|D8202|(% colspan="3" %)Reserved| | |
1240 |M8203|(% colspan="2" %)C203 Control|O|O|D8203|(% colspan="3" %)Reserved| | |
1241 |M8204|(% colspan="2" %)C204 Control|O|O|D8204|(% colspan="3" %)Reserved| | |
1242 |M8205|(% colspan="2" %)C205 Control|O|O|D8205|(% colspan="3" %)Reserved| | |
1243 |M8206|(% colspan="2" %)C206 Control|O|O|D8206|(% colspan="3" %)Reserved| | |
1244 |M8207|(% colspan="2" %)C207 Control|O|O|D8207|(% colspan="3" %)Reserved| | |
1245 |M8208|(% colspan="2" %)C208 Control|O|O|D8208|(% colspan="3" %)Reserved| | |
1246 |M8209|(% colspan="2" %)C209 Control|O|O|D8209|(% colspan="3" %)Reserved| | |
1247 |M8210|(% colspan="2" %)C210 Control|O|O|D8210|(% colspan="3" %)Reserved| | |
1248 |M8211|(% colspan="2" %)C211 Control|O|O|D8211|(% colspan="3" %)Reserved| | |
1249 |M8212|(% colspan="2" %)C212 Control|O|O|D8212|(% colspan="3" %)Reserved| | |
1250 |M8213|(% colspan="2" %)C213 Control|O|O|D8213|(% colspan="3" %)Reserved| | |
1251 |M8214|(% colspan="2" %)C214 Control|O|O|D8214|(% colspan="3" %)Reserved| | |
1252 |M8215|(% colspan="2" %)C215 Control|O|O|D8215|(% colspan="3" %)Reserved| | |
1253 |M8216|(% colspan="2" %)C216 Control|O|O|D8216|(% colspan="3" %)Reserved| | |
1254 |M8217|(% colspan="2" %)C217 Control|O|O|D8217|(% colspan="3" %)Reserved| | |
1255 |M8218|(% colspan="2" %)C218 Control|O|O|D8218|(% colspan="3" %)Reserved| | |
1256 |M8219|(% colspan="2" %)C219 Control|O|O|D8219|(% colspan="3" %)Reserved| | |
1257 |M8220|(% colspan="2" %)C220 Control|O|O|D8220|(% colspan="3" %)(((
1258 D8220=1 to enable the new filtering methods (four points constitute a set of filter). When use new filtering methods, the filter time which set by D8020 is not valid. And before using this filtering methods, users need to set the filtering time for each X terminals (D8221~~D8228), Filter time unit is ms.
1259
1260 Note: This filter method only works on CPU IO, the IO in extension module is not invalid.
1261 )))|O|O|
1262 |M8221|(% colspan="2" %)C221 Control|O|O|D8221|(% colspan="3" %)(((
1263 Low bits are for setting filter time of X0~~X3;
1264
1265 High bits are for setting filter time of X4~~X7
1266
1267 Unit is ms
1268 )))|O|O|
1269 |M8222|(% colspan="2" %)C222 Control|O|O|D8222|(% colspan="3" %)(((
1270 Low bits are for setting filter time of X10~~X13;
1271
1272 High bits are for setting filter time of X14~~X17
1273
1274 Unit is ms
1275 )))|O|O|
1276 |M8223|(% colspan="2" %)C223 Control|O|O|D8223|(% colspan="3" %)(((
1277 Low bits are for setting filter time of X20~~X23;
1278
1279 High bits are for setting filter time of X24~~X27
1280
1281 Unit is ms
1282 )))|O|O|
1283 |M8224|(% colspan="2" %)C224 Control|O|O|D8224|(% colspan="3" %)(((
1284 Low bits are for setting filter time of X30~~X33;
1285
1286 High bits are for setting filter time of X34~~X37
1287
1288 Unit is ms
1289 )))|O|O|
1290 |M8225|(% colspan="2" %)C225 Control|O|O|D8225|(% colspan="3" %)(((
1291 Low bits are for setting filter time of X40~~X43;
1292
1293 High bits are for setting filter time of X44~~X47
1294
1295 Unit is ms
1296 )))|O|O|
1297 |M8226|(% colspan="2" %)C226 Control|O|O|D8226|(% colspan="3" %)(((
1298 Low bits are for setting filter time of X50~~X53;
1299
1300 High bits are for setting filter time of X54~~X57
1301
1302 Unit is ms
1303 )))|O|O|
1304 |M8227|(% colspan="2" %)C227 Control|O|O|D8227|(% colspan="3" %)(((
1305 Low bits are for setting filter time of X60~~X63;
1306
1307 High bits are for setting filter time of X64~~X67
1308
1309 Unit is ms
1310 )))|O|O|
1311 |M8228|(% colspan="2" %)C228 Control|O|O|D8228|(% colspan="3" %)(((
1312 Low bits are for setting filter time of X70~~X73;
1313
1314 High bits are for setting filter time of X74~~X77
1315
1316 Unit is ms
1317 )))|O|O|
1318 |M8229|(% colspan="2" %)C229 Control|O|O|D8229|(% colspan="3" %)Reserved| | |
1319 |M8230|(% colspan="2" %)C230 Control|O|O|D8230|(% colspan="3" %)Reserved| | |
1320 |M8231|(% colspan="2" %)C231 Control|O|O|D8231|(% colspan="3" %)Reserved| | |
1321 |M8232|(% colspan="2" %)C232 Control|O|O|D8232|(% colspan="3" %)Reserved| | |
1322 |M8233|(% colspan="2" %)C233 Control|O|O|D8233|(% colspan="3" %)Reserved| | |
1323 |M8234|(% colspan="2" %)C234 Control|O|O|D8234|(% colspan="3" %)Reserved| | |
1324 |M8235|(% rowspan="11" %)One phase one directional|C235 Control|O|O|D8235|(% colspan="3" %)Reserved| | |
1325 |M8236|C236 Control|O|O|D8236|(% colspan="3" %)Reserved| | |
1326 |M8237|C237 Control|O|O|D8237|(% colspan="3" %)Reserved| | |
1327 |M8238|C238 Control|O|O|D8238|(% colspan="3" %)Reserved| | |
1328 |M8239|C239 Control|O|O|D8239|(% colspan="3" %)Reserved| | |
1329 |M8240|C240 Control|O|O|D8240|(% colspan="3" %)Reserved| | |
1330 |M8241|C241 Control|O|O|D8241|(% colspan="3" %)Reserved| | |
1331 |M8242|C242 Control|O|O|D8242|(% colspan="3" %)Reserved| | |
1332 |M8243|C243 Control|O|O|D8243|(% colspan="3" %)Reserved| | |
1333 |M8244|C244 Control|O|O|D8244|(% colspan="3" %)Reserved| | |
1334 |M8245|C245 Control|O|O|D8245|(% colspan="3" %)Reserved| | |
1335 |M8246|(% rowspan="5" %)2 phase bi-directional|C246 Control|O|O|D8246|(% colspan="3" %)Reserved| | |
1336 |M8247|C247 Control|O|O|D8247|(% colspan="3" %)Reserved| | |
1337 |M8248|C248 Control|O|O|D8248|(% colspan="3" %)Reserved| | |
1338 |M8249|C249 Control|O|O|D8249|(% colspan="3" %)Reserved| | |
1339 |M8250|C250 Control|O|O|D8250|(% colspan="3" %)Reserved| | |
1340 |M8251|(% rowspan="5" %)A/B phase|C251 Control|O|O|D8251|(% colspan="3" %)Reserved| | |
1341 |M8252|C252 Control|O|O|D8252|(% colspan="3" %)Reserved| | |
1342 |M8253|C253 Control|O|O|D8253|(% colspan="3" %)Reserved| | |
1343 |M8254|C254 Control|O|O|D8254|(% colspan="3" %)Reserved| | |
1344 |M8255|C255 Control|O|O|D8255|(% colspan="3" %)Reserved| | |