Changes for page 08 High speed process
Last modified by Jett on 2025/10/27 11:06
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... ... @@ -130,6 +130,11 @@ 130 130 131 131 The operation principle of the HSCR command is similar to that of the HSCS instruction, except that the HSCR output action is just opposite to the HSCS instruction, i.e., when the counter value is equal, the specified output will be reset. 132 132 133 +(% class="box infomessage" %) 134 +((( 135 +**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time. 136 +))) 137 + 133 133 = **6.8.5 DHSCS instruction** = 134 134 135 135 **Instruction description** ... ... @@ -167,6 +167,11 @@ 167 167 168 168 LX3V could use interrupt pointers I010 through I060 (6 points) as destination devices (D). This enables interrupt routines to be triggered directly when the value of the specified high speed counter reaches the value in the HSCS instruction. When (D) is between I010~~I060, the subprogram for interrupting 0~~5 in the high-speed counter needs to be initiated. 169 169 175 +(% class="box infomessage" %) 176 +((( 177 +**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time. 178 +))) 179 + 170 170 = **6.8.6 DHSZ instruction** = 171 171 172 172 **Instruction description** ... ... @@ -195,7 +195,10 @@ 195 195 (% style="text-align:center" %) 196 196 [[image:7-7 High speed process_html_5a7b133dc73dd30f.jpg||height="224" width="500" class="img-thumbnail"]] 197 197 198 -= **6.8.7 SPD instruction** = 208 +(% class="box infomessage" %) 209 +((( 210 +**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time. 211 +))) 199 199 200 200 **Instruction description** 201 201