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Changes for page 08 High speed process

Last modified by Jett on 2025/10/27 11:06
From version 3.1
edited by Jett
on 2025/10/27 11:05
Change comment: There is no comment for this version
To version 1.1
edited by Wecon
on 2025/09/03 21:03
Change comment: Imported from XAR

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1 -XWiki.2454238480
1 +XWiki.Wecon
Content
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130 130  
131 131  The operation principle of the HSCR command is similar to that of the HSCS instruction, except that the HSCR output action is just opposite to the HSCS instruction, i.e., when the counter value is equal, the specified output will be reset.
132 132  
133 -(% class="box infomessage" %)
134 -(((
135 -**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time.
136 -)))
137 -
138 138  = **6.8.5 DHSCS instruction** =
139 139  
140 140  **Instruction description**
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172 172  
173 173  LX3V could use interrupt pointers I010 through I060 (6 points) as destination devices (D). This enables interrupt routines to be triggered directly when the value of the specified high speed counter reaches the value in the HSCS instruction. When (D) is between I010~~I060, the subprogram for interrupting 0~~5 in the high-speed counter needs to be initiated.
174 174  
175 -(% class="box infomessage" %)
176 -(((
177 -**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time.
178 -)))
179 -
180 180  = **6.8.6 DHSZ instruction** =
181 181  
182 182  **Instruction description**
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205 205  (% style="text-align:center" %)
206 206  [[image:7-7 High speed process_html_5a7b133dc73dd30f.jpg||height="224" width="500" class="img-thumbnail"]]
207 207  
208 -(% class="box infomessage" %)
209 -(((
210 -**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time.
211 -)))
198 += **6.8.7 SPD instruction** =
212 212  
213 213  **Instruction description**
214 214