08 High speed process

Standard PLC operation processes output and input status between the END instruction of one program scould and step 0 of the following program scould. If an immediate update of the I/O device status is required, the REF instruction is used.

22

23

REF could be used between the instruction FOR~~ NEXT or CJ.

24

25

REF could be used in the interrupt subprogram to refresh the input information and the output result.

26

27

The delay of the input port state depends on the filter time of the input device. X0 to X7 have the digital filter function, the filter time is between 0 and 60 ms, the other IO ports are hardware filter that the filter time is 10 ms. The specific parameter you need to refer to the PLC manual.

28

29

The delay of the output port state change depends on the response time of the output element, such as relay. The output contact will not act until the response time of the relay or transistor is over.

30

31

The response latency of the relay output type plc is about 10 ms (max :20ms),the high speed output port of the transistor plc is about 10 us, for the common output port of the transistor plc is about 0.5 ms. The specific parameter you need to refer to the PLC manual.

**Program example**

(% style="text-align:center" %)

36

[[image:7-7 High speed process_html_db0844dad4d33f1.jpg||height="65" width="300" class="img-thumbnail"]]

37

38

During the operation, once X20 is ON, the state of the input port X0 to X17 will be read immediately, the input signal will be refreshed and there is no input delay.

39

40

(% style="text-align:center" %)

41

[[image:7-7 High speed process_html_f11c740cefc73df8.jpg||height="66" width="300" class="img-thumbnail"]]

42

43

During the operation, once X20 is ON, the state of the output port Y0 to Y17 will be read immediately, the output signal will be refreshed immediately rather than until the END instruction.

44

45

= **6.8.2 REFF instruction** =

46

47

**Instruction description**

48

49

(% class="table-bordered" %)

50

51

|REFF|(% rowspan="2" %)Inputs are refreshed, and their input filters are reset to the newly designated value|16|No|(% rowspan="2" %)REFF n|7

52

|REFFP|16|No|7

53

54

n is the filter time for X0 ~~ X7 input port.

55

56

X0~~X7 use digital filters, the default filter time is set by the D8020. D8020 could be changed to 0 ~~ 60ms by REFF instruction. The remaining X ports only have hardware RC filter that the filter time is about 10ms and couldn’t be changed.

57

58

When using the interrupts or high speed counting, the filter time of the related port reduce to minimum automatically. The unrelated ports stay as it was.

59

60

User could also use MOV instruction to change the value of D8020.

61

62

(% class="table-bordered" %)

63

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

64

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

65

|n|(% colspan="16" %)Constant, n=0~~60, the unit is ms

66

| | | | | | | | | | | | | | | | |

**Program example**

(% style="text-align:center" %)

71

[[image:7-7 High speed process_html_bcb03d347f659e21.jpg||height="237" width="300" class="img-thumbnail"]]

72

73

When X10 is triggered, the filter time of X0~~X7 is 5ms, when X10 is OFF, The filter time of X0~~ X7 is 15 ms.

74

75

= **6.8.3 MTR instruction** =

76

77

**Instruction description**

78

79

(% class="table-bordered" %)

80

81

|MTR|Multiplexes a bank of inputs into a number of sets of devices. Could only be used once.|16|No|MTR S D,,1,, D,,2,, n|9

82

83

This instruction is only for transistor plc. This instruction allows a selection of 8 consecutive input devices (head address S) to be used multiple times, i.e. each physical input has more than one, separate and quite different (D,,1,,) signal being processed. The result is stored in a matrix-table (head address D,,2,,). “n” is the number of scouldning column in matrix.

84

85

(% class="table-bordered" %)

86

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

87

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

88

|S|√| | | | | | | | | | | | | | |

89

|D1| |√| | | | | | | | | | | | | |

90

|D2| |√|√|√| | | | | | | | | | | |

91

|n|(% colspan="16" %)Constant, n=2~~8

**Program example**

(% style="text-align:center" %)

96

[[image:7-7 High speed process_html_ec8c75f5060253a5.jpg||height="54" width="400" class="img-thumbnail"]]

**The wiring:**

When output Y30 is ON only those inputs in the first bank are read. These results are then stored; in this example, auxiliary coils M10 to M17. The second step involves Y30 going OFF and Y31coming ON. This time only inputs in the second bank are read. These results are stored in devices M20 to M27. The last step of this example has Y31 going OFF and Y32 coming ON. This then allows all of the inputs in the second bank to be read and stored in devices M20 to M27. The processing of this instruction example would take 20 × 2 = 40 msec.

101

102

A scouldning input with a maximum of 64 points could be achieved using 8-point X output and 8-point transistor Y output. But it is not suitable for high speed input operations because it needs a time of 20 ms,8 line= 160 ms to read each input. Therefore, the ports after X20 are typically used as the scouldning inputs. This instruction is allowed to be used only once in the program.

103

104

(% style="text-align:center" %)

105

[[image:7-7 High speed process_html_d712c907a19ec1b6.jpg||height="458" width="600" class="img-thumbnail"]]

106

107

= **6.8.4 DHSCR instruction** =

108

109

**Instruction description**

110

111

(% class="table-bordered" %)

112

113

|DHSCR|Resets the selected output when the specified high speed counter equals the test value|32|No|DHSCR S,,1,, S,,2,, D|13

114

115

The HSCR compares the current value of the selected high speed counter (S,,2,,) against a selected value (S,,1,,). When the counters current value changes to a value equal to S1, the device specified as the destination (D) is reset.

116

117

(% class="table-bordered" %)

118

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

119

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

120

|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

121

|S,,2,,| | | | | | | | | | | | |√| | |

122

|D| |√|√|√| | | | | | | | | | | |

**Program example**

(% style="text-align:center" %)

127

[[image:7-7 High speed process_html_d4622aff42a2be76.jpg||height="157" width="600" class="img-thumbnail"]]

128

129

In the example above, Y10 would be reset only when C255’s value stepped from 199 to 200 or from 201 to 200. If the current value of C255 was forced to equal 200 by test techniques, output Y10 would NOT reset.

130

131

The operation principle of the HSCR command is similar to that of the HSCS instruction, except that the HSCR output action is just opposite to the HSCS instruction, i.e., when the counter value is equal, the specified output will be reset.

132

133

= **6.8.5 DHSCS instruction** =

134

135

**Instruction description**

136

137

(% class="table-bordered" %)

138

139

|DHSCS|Sets the selected output when the specified high speed counter value equals the test value|32|No|DHSCS S,,1,, S,,2,, D|13

140

141

The HSCS set, compares the current value of the selected high speed counter (S,,2,,) against a selected value (S,,1,,). When the counters current value changes to a value equal to S1 the device specified as the destination (D) is set ON.

142

143

It is recommended that the drive input used for the high speed counter functions; HSCS, HSCR, HSCZ is the special auxiliary RUN contact M8000.

144

145

If more than one high speed counters function is used for a single counter the selected flag devices (D) should be kept within 1 group of 8 devices, i.e. Y0-7, M10-17.

146

147

All high speed counter functions use an interrupt process; hence, all destination devices (D) are updated immediately.

148

149

(% class="table-bordered" %)

150

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

151

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

152

|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

153

|S,,2,,| | | | | | | | | | | | |√| | |

154

|D| |√|√|√| | | | | | | | | | | |

**Program example**

**Example 1:**

(% style="text-align:center" %)

161

[[image:7-7 High speed process_html_3aace41414766cc2.jpg||height="156" width="600" class="img-thumbnail"]]

**Example 2:**

(% style="text-align:center" %)

166

[[image:7-7 High speed process_html_89438e3da1774961.jpg||height="193" width="300" class="img-thumbnail"]]

167

168

LX3V could use interrupt pointers I010 through I060 (6 points) as destination devices (D). This enables interrupt routines to be triggered directly when the value of the specified high speed counter reaches the value in the HSCS instruction. When (D) is between I010~~I060, the subprogram for interrupting 0~~5 in the high-speed counter needs to be initiated.

169

170

= **6.8.6 DHSZ instruction** =

171

172

**Instruction description**

173

174

(% class="table-bordered" %)

175

176

|DHSZ|The current value of a high speed counter is checked against a specified range|32|No|DHSZ S,,1,, S,,2,, S D|17

177

178

This instruction works in exactly the same way as the standard ZCP. The only difference is that the device being compared is a high speed counter (specified as S). Also, all of the outputs (D) are updated immediately due to the interrupt operation of the DHSZ. It should be remembered that when a device is specified in operand D it is in fact a head address for 3 consecutive devices. Each one is used to represent the status of the current comparison.

179

180

* S,,1,, is the lower limit; S,,1,, must be equal to or less than S2.

181

* S,,2,, is the upper limit.

182

* S must be C235~~C255, because C235~~C255 are 32bit counter, so user must use DHSZ not HSZ.

183

* D is for storing comparison result. When it is Y0~~Y17 or M or S, there is no latency. For other output port, the output will not be executed until program END.

184

185

(% class="table-bordered" %)

186

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

187

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

188

|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

189

|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

190

|S| | | | | | | | | | | | |√| | |

191

|D| |√|√|√| | | | | | | | | | | |

**Program example**

(% style="text-align:center" %)

196

[[image:7-7 High speed process_html_5a7b133dc73dd30f.jpg||height="224" width="500" class="img-thumbnail"]]

197

198

= **6.8.7 SPD instruction** =

199

200

**Instruction description**

201

202

(% class="table-bordered" %)

203

204

|SPD|Detects the number of ‘encoder’ pulses in a given time frame. Results could be used to calculate speed|16|No|SPD S,,1,, S,,2,, D|7

205

206

The number of pulses received at S,,1,, are counted and stored in D+1; this is the current count value. The counting takes place over a set time frame specified by S,,2,, in msec. The time remaining on the current ‘timed count’, is displayed in device D+2.

207

208

The number of counted pulses (of S,,1,,) from the last timed count is stored in D.

209

210

(% class="table-bordered" %)

211

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

212

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

213

|S,,1,,|√| | | | | | | | | | | | | | |

214

|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

215

|D| | | | | | | | | | | |√|√|√|√|√

**Program example**

(% style="text-align:center" %)

220

[[image:7-7 High speed process_html_82860708e693606a.jpg||height="77" width="400" class="img-thumbnail"]]

221

222

X0 is the pulse input port.

223

224

D0 defines the set time frame.

225

226

Current count value, device D10

227

228

Accumulated/ last count value, device D11

229

230

Current time remaining in msec, device D12

231

232

= **6.8.8 PLSY instruction** =

233

234

**Instruction description**

235

236

(% class="table-bordered" %)

237

238

|PLSY|(% rowspan="2" %)Outputs a specified number of pulses at a set frequency|16|No|(% rowspan="2" %)PLSY S,,1,, S,,2,, D|7

239

|DPLSY|32|Yes|13

240

241

A specified quantity (S2) of pulses is output through device D at a specified frequency S1. This instruction is used in situations where the quantity of outputs is of primary concern.

242

243

For PLSY, S1’s range is 1~~32767 Hz, for DPLSY, S1’s range is 1~~200000 Hz.

244

245

For PLSY, S2’s range is 1~~32767, for DPLSY, S1’s range is 1~~2147483647. If S2 is 0, it means there is no limitation for the output pulse quantity.

246

247

For LX3V/3VP/3VE, D could be Y0~~Y3. For LX3V (1s) type, D could only be Y0 or Y1.

248

249

(% class="table-bordered" %)

250

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

251

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

252

|S,,1,,| | | | | | | |√|√|√|√|√|√|√|√|√

253

|S,,2,,| | | | | | | |√|√|√|√|√|√|√|√|√

254

|D| |√| | | | | | | | | | | | | |

**Program example**

(% style="text-align:center" %)

259

[[image:7-7 High speed process_html_96c6d839f94ba458.jpg||height="61" width="400" class="img-thumbnail"]]

260

261

In the example, when X0 is OFF, the output becomes 0 too, when X0 becomes ON again it will react initially.

262

263

A single pulse is described as having a 50% duty cycle. This means it is ON for 50% of the pulse and OFF for the 50% of the pulse. The actual is controlled by interrupt handling, i.e. the output cycle is not affected by the scould time of the program.

264

265

The pulse completion flag (M8029) is set when the PLSY instruction is done.

266

267

**The related variable in the PLSY:**

268

269

* D8141 (high byte), D8140 (low byte): Y000 the count of output pulse, when the direction is reverse, Y000 decrease. (32-bits)

270

* D8143 (high byte), D8142 (low byte): Y001 the count of output pulse, when the direction is reverse, Y000 decrease. (32-bits)

271

* D8151 (high byte), D8150 (low byte): Y002 the count of output pulse, when the direction is reverse, Y000 decrease.(32-bit)

272

* D8153 (high byte), D8152 (low byte): Y003 the count of output pulse, when the direction is reverse, Y000 decrease.(32-bit)

273

* M8145: Y000 stop output pulse (immediately)

274

* M8146: Y001 stop output pulse (immediately)

275

* M8152: Y002 stop output pulse (immediately)

276

* M8153: Y003 stop output pulse (immediately)

277

* M8147: Y000 monitor in the output pulse(BUSY/READY)

278

* M8148: Y001 monitor in the output pulse(BUSY/READY)

279

* M8149: Y002 monitor in the output pulse(BUSY/READY)

280

* M8150: Y003 monitor in the output pulse(BUSY/READY)

281

282

= **6.8.9 PWM instruction** =

283

284

**Instruction description**

285

286

(% class="table-bordered" %)

287

288

|PWM|Generates a pulse train with defined pulse characteristics|16|No|PWM S,,1,, S,,2,, D|7

289

290

Only transistor type PLC could support PWM instruction. S,,1,, defines the width of the pulse, S,,2,, defines the pulse period, and D defines the output port. For LX3V (1S firmware), the output port could be Y0 or Y1, for LX3V (2N firmware), the output port could be Y0~~Y3.

291

292

The output port couldn’t be the same with PLSY or PLSR instruction.

293

294

S,,1,, <= S,,2,,, the setting range of S,,1,, is 0~~32767 ms. S,,2,, ranges from 1 to 32767ms.

295

296

(% class="table-bordered" %)

297

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

298

|**X**|**Y**|**M**|**S**|**K**|**H**|**E**|**KnX**|**KnY**|**KnM**|**KnS**|**T**|**C**|**D**|**V**|**Z**

299

|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

300

|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

301

|D| |√| | | | | | | | | | | | | |

**Program example**

(% style="text-align:center" %)

306

[[image:7-7 High speed process_html_d3d534d5d0b8fb51.jpg||height="197" width="500" class="img-thumbnail"]]

307

308

**Thousand-ratio pattern**

309

310

The thousand-ratio pattern: the thousand-ratio pattern is to divide the periodic parameters evenly equal to 1000. The user sets correspond to the control bit ON for thousand-ratio pattern as follows:

311

312

(% class="table-bordered" %)

313

|**Outputs**|Y0|Y1|Y2|Y3

314

|**Control bits**|M8134|M8135|M8136|M8137

**[Example]**

(% style="text-align:center" %)

319

[[image:7-7 High speed process_html_cef6612aa705d4ce.jpg||height="262" width="500" class="img-thumbnail"]]

320

321

Cycle set to 100ms, duty ratio if set to 500, then output to high level is 50ms, low level is 50ms; duty ratio if set to 100, then output to high level is 10ms, low level is 90ms; duty ratio if set to 900, then output high level is 90ms, low level is 10ms;

322

323

**Calculation formula:** t (ms) =T0 (ms) *K/1000

324

325

High level time (ms) = cycle time (ms) * duty ratio/1000

326

327

Low level time (ms) = cycle time (ms) – high level time (ms)

328

329

= **6.8.10 PLSR instruction** =

330

331

**Instruction description**

332

333

(% class="table-bordered" %)

334

335

|(% style="width:93px" %)PLSY|(% rowspan="2" style="width:535px" %)Outputs a specified number of pulses at a set frequency|16|No|(% rowspan="2" %)PLSY S,,1,, S,,2,, S,,3,, D|7

336

|(% style="width:93px" %)DPLSY|32|Yes|17

337

338

Because of the nature of the high speed output, transistor output units should be used with this instruction. Relay outputs will suffer from a greatly reduced life and will cause false outputs to occur due to the mechanical ‘bounce’ of the contacts.

339

340

* S,,1,,: The maximum frequency, the range is 10~~100,000Hz

341

* S,,2,,: A specified quantity of output pulses, 16-bit operation: 110 to 32,767 pulses, 32-bit operation: 110 to 2,147,483,647 pulses. If it was less than 110, PLC couldn’t output pulse;

342

* S,,3,,: The acceleration time, the range is 10~~32,000 (ms).

343

* D: output port, for LX3V/3VP/3VE, D could be Y0~~Y3, for LX3V (1s) type, D could only be Y0 or Y1.

344

345

(% class="table-bordered" %)

346

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

347

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

348

|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

349

|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

350

|S,,3,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

351

|D| |√| | | | | | | | | | | | | |

**Program example**

(% style="text-align:center" %)

356

[[image:7-7 High speed process_html_3b46454b18532a23.jpg||height="103" width="500" class="img-thumbnail"]]

357

358

(% style="text-align:center" %)

359

[[image:7-7 High speed process_html_1f699763d7829b6.jpg||height="310" width="700" class="img-thumbnail"]]

360

361

The special registers corresponding to each output port are listed as follow:

362

363

(% class="table-bordered" %)

364

|(% colspan="2" style="width:149px" %)**Register**|(% style="width:523px" %)**Definition**|**Remarks**

365

|D8140|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y0 port set in the PLSY or PLSR instruction|(% rowspan="10" %)Applicable instructions: use DMOV K0 D81xx to perform clear operation

366

|D8140|(% style="width:91px" %)High byte

367

|D8142|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y1 port set in the PLSY or PLSR instruction

368

|D8143|(% style="width:91px" %)High byte

369

|D8150|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y2 port set in the PLSY or PLSR instruction

370

|D8151|(% style="width:91px" %)High byte

371

|D8152|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y3 port set in the PLSY or PLSR instruction

372

|D8153|(% style="width:91px" %)High byte

373

|D8136|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Accumulative value of the number of the pulses already output to Y0 and Y1

374

|D8137|(% style="width:91px" %)High byte

375

376

The output frequency range of this instruction is 10 ~~ 100, 000Hz. When it is out of range, it will be automatically converted into the range and then executed. However, the actual output frequency depends on the following formula.

Output frequency=

(% style="text-align:center" %)

381

[[image:7-7 High speed process_html_264371750fbe73ba.jpg||height="27" width="400" class="img-thumbnail"]]

382

383

The frequency of the initial and final stages of acceleration should not be lower than the result of the above formula.

384

385

Example: Maximum speed is 50,000, acceleration /deceleration time is 100ms.

386

387

[[image:7-7 High speed process_html_19453a8b227b5316.jpg]] = 500 (Hz)

388

389

When maximum frequency S1 is specified to 50000Hz, the actual output frequency at the early stage of acceleration and at the late stage of deceleration is 500Hz.

390

391

(% style="text-align:center" %)

392

[[image:7-7 High speed process_html_5692a599dd293f8a.jpg||height="242" width="600" class="img-thumbnail"]]

1. **Note for use**

* The instruction is executed in an interruption way; therefore, it will not be influenced by the scouldning cycle;

397

* When the instruction power flow is OFF, the deceleration stop is active; when the power flow is changed from OFF→ON, the pulse output process starts over again.

398

* During the pulse output process, changing the operand has no effect on this output, and the modified content will take effect when the instruction is executed next time.

399

* Special auxiliary coil M8029 is turned ON when the specified number of pulses has been completed. The pulse count and completion flag (M8029) are reset when the PLSY instruction is de-energized. If “0" (zero) is specified, the PLSY instruction will continue generating pulses for as long as the instruction is energized.

400

* The process couldn’t be repeated with the output port number of the PWM instruction.

401

402

= **6.8.11 PLSR2 instruction** =

403

404

**1) Instruction description**

405

406

(% class="table-bordered" %)

407

408

|PLSR2|Multi-speed pulse output|16|No |PLSR2 S,,1,,D,,1,,D,,2,,|7

409

410

(% class="table-bordered" %)

411

|(% rowspan="2" %)**Operand** |(% colspan="4" %)**Bit device **|(% colspan="12" %)**Word device**

412

|X|Y|M|S|K|H |E|KnX|KnY|KnM |KnS|T |C|D|V|Z

413

|S ,,1,,| | | | | | | | | | | | | |v| |

414

|D,,1,,| |v| | | | | | | | | | | | | |

415

|D,,2,,| |v|v|v| | | | | | | | | | | |

416

417

This instruction is only valid for LX3VP series PLC.

418

419

PLSR2 instruction sets parameters on table list, and generates relative/ absolute position pulse according specified port, frequency, direction and ramp time. so that servo actuator gives the offset on the motion based on the current position. Only transistor output PLC supports this instruction.

420

421

S,,1,,: Register parameter, Dn is the start register of the specified register segment;

422

423

D,,1,, Pulse output port, designated Y0-Y3;

424

425

D,,2,,: The direction or position variable output port, ON: indicates the operating forward; otherwise, run in reverse.

426

427

428

(% style="text-align:center" %)

429

[[image:1620463452720-887.png||height="77" width="400" class="img-thumbnail"]]

430

431

432

(% class="table-bordered" %)

|(((

**S,,1,,**

**Register offset**

)))|**Content**|**Description**

438

|S,,1,,+0|Table flag|Retention

439

|S,,1,,+1|Table version|Retention

440

|S,,1,,+2|Pulse total number of segments|1-12

441

|S,,1,,+3|Acceleration and deceleration mode|0: First acceleration mode; 1: Later acceleration mode

442

|S,,1,,+4|Acceleration time|50-32000ms

443

|S,,1,,+5|Deceleration time|50-32000ms

444

|S,,1,,+6|Default frequency|10HZ-200KHZ

445

|S,,1,,+7| |

446

|S,,1,,+8|Relative / absolute mode|0: relative; 1: Absolute

447

|S,,1,,+ 9-** **S,,1,,+19|Retention|Retention

448

|S,,1,,+20|First segment pulse frequency|10HZ-200KHZ

449

|S,,1,,+21| |

450

|S,,1,,+22|First segment total number of pulses|No

451

|S,,1,,+23| |

452

|S,,1,,+24|First segment wait condition|(((

453

0: pulse transmission is completed;

1: waiting time;

2: wait signal;

3: Trigger signal. (With [waiting condition] and [Pending Register] with use)

460

)))

461

|S,,1,,+25|First segment Wait register type|(((

462

Waiting condition register type and relationship:

463

464

Pulse transmission completion: None

465

466

Waiting time: = 0: D register; = 1: constant;

467

468

Wait signal: = 0: X register; = 1: M bit register;

469

470

Trigger: = 0: X register; = 1: M bit register.

471

)))

472

|S,,1,,+26|First segment constant value / standby register number|No

473

|S,,1,,+27| |

474

|S,,1,,+28|Retention|Retention

475

|S,,1,,+29|Retention|Retention

476

|...|...|...

477

|S,,1,,+ 10 + n * 10|The N-th pulse frequency|10HZ - 200KHZ

478

479

**2) Programming example**

480

481

The demonstration shown below is parameters settings for 4 segments pulse starting with D0, the acceleration time is 100 ms from lowest frequency to the default frequency(100,000Hz), the deceleration time is 100 ms, it is in absolute mode.

482

483

484

(% style="text-align:center" %)

485

[[image:1620463472811-235.png||height="374" width="700" class="img-thumbnail"]]

486

487

The number of pulses of the frequency of each segment and the wait condition as follows:

488

489

(% class="table-bordered" %)

490

491

|1|10,000|10,000|waiting time|K100

492

|2|20,000|20,000|Waiting for the signal|M1

493

|3|15,000|40,000|Trigger|X1

494

|4|30,000|60,000|No wait condition|K0

495

496

Configured in accordance with parameters:

497

498

(% style="text-align:center" %)

499

[[image:1620463489594-301.png||height="1128" width="700" class="img-thumbnail"]]

500

501

**3) Parameter Description**

502

503

1) ** **S,,1,,+2: pulse for setting the number of stages (word), a data range 1-12, it means support 1-12 segments;

504

505

2) Acceleration and deceleration modes

506

507

S,,1,,+3: to set the acceleration and deceleration patterns (words), is set to 0 before the addition mode is set to 1 after addition mode, wherein:

508

509

a) Early acceleration mode: When a multi-stage pulse is applied and the first stage pulse finished according to first stage frequency, the next stage frequency has been accelerated in advance.

510

511

b) Later acceleration mode: When a multi-stage pulse is applied and the first stage pulse finished according to first stage frequency, the next stage frequency just begin to accelerate.

512

513

For example, now need three stages of pulse, the first pulse frequency is 2000Hz, the number of pulse is 2000, the second pulse frequency is 4000Hz, the number of pulse is 4000, and the third pulse frequency is 6000Hz, the number of pulse is 6000.

514

515

**Early acceleration mode as below:**

516

517

(% style="text-align:center" %)

518

[[image:1620463500954-987.png||height="305" width="500" class="img-thumbnail"]]

519

520

**Later acceleration mode as below:**

521

522

(% style="text-align:center" %)

523

[[image:1620463504313-304.png||height="303" width="500" class="img-thumbnail"]]

524

525

(3) Acceleration time, deceleration time and default frequency

526

527

S,,1,,+14 (single word) is the acceleration time;

528

529

S,,1,,+5 (single word) deceleration time;

530

531

S,,1,,+6 (double word) default frequency;

532

533

The output frequency range of this instruction is 10 ~~ 200, 000Hz. When the maximum speed(acceleration and deceleration) beyond this range,PLC will automatically convert (up or down) to the able range and perform.

534

535

The acceleration time refers to the time from the base frequency to the default frequency, and the deceleration time refers to the time from the default frequency to the base frequency.

536

537

538

(% style="text-align:center" %)

539

[[image:1620463515599-686.png||height="509" width="700" class="img-thumbnail"]]

540

541

(4) Relative, absolute mode

542

543

S1+8 (single word) is used in setting the parameters of pulse configuration for relative mode or absolute mode. When it is set to (relative mode), that means the pulse number and current value register is relative position. Set to 1 (absolute mode), that means pulse number and current value register is absolute position.

544

545

The corresponding relationship between the output port and the current pulse value register is as follows:

546

547

l [Y000] output, the current pulse value register is [D8141 (high byte), D8140 (low byte)] (32 bits)

548

549

l [Y001] output, the current pulse value register is [D8143 (high bytes), D8142 (low bytes)] (32 bits)

550

551

l [Y002] output, the current pulse value register is [D8151 (high bytes), D8150 (low bytes)] (32 bits)

552

553

l [Y003] output, the current pulse value register is [D8153 (high bytes), D8152 (low bytes)] (32 bits)

**For example**

Now need three stages of pulse, the first pulse frequency is 2000Hz, the number of pulse is 2000, the second pulse frequency is 4000Hz, the number of pulse is 4000, and the third pulse frequency is 6000Hz, the number of pulse is 6000Hz.

558

559

The corresponding mode settings are as follows:

560

561

(% class="table-bordered" %)

562

563

|1|2000|2000|No waiting condition|K0

564

|2|4000|4000|No waiting condition|K0

565

|3|6000|6000|No waiting condition|K0

566

567

PLC ladder setting as below:

568

569

(% style="text-align:center" %)

570

[[image:1620463634015-908.png||height="927" width="700" class="img-thumbnail"]]

571

572

Absolute mode setting as below:

573

574

(% class="table-bordered" %)

575

576

|1|2000|2000|No waiting condition|K0

577

|2|4000|4000|No waiting condition|K0

578

|3|6000|6000|No waiting condition|K0

579

580

PLC ladder setting as below:

581

582

(% style="text-align:center" %)

583

[[image:1620463530261-493.png||height="927" width="700" class="img-thumbnail"]]

584

585

**✎Note: **absolute mode, if the current position of the same segment with the next paragraph, it is considered the next paragraph does not exist, at some speed will drop to zero.

586

587

The following table shows the absolute mode, the first segment a second segment of the same pulse position where:

588

589

(% class="table-bordered" %)

590

591

|1|2000|2000|No waiting condition|K0

592

|2|3000|2000|No waiting condition|K0

593

|3|2000|3000|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

599

[[image:1620463650482-502.png||height="224" width="300" class="img-thumbnail"]]

(5) Wait condition

S,,1,,+ 14 + 10 * N (word) is the wait condition paragraph N, S,,1,,+ 15 + 10 * N (word) register type waiting, S,,1,,+ 16 + 10 * N (double word) waiting ID register / constant value. Wait condition = 0 is no wait condition, when latency = 1, 2 = wait for signals, the trigger signal = 3.

604

605

Wait condition and waiting and waiting for the register number register / constant value used in conjunction.

606

607

a) No wait condition:

608

609

S,,1,,+ 14 + 10 * N (word) = 0 is no wait condition. After performing the set pulse number of this paragraph, immediately jump to a specified later burst.

610

611

**Example: **current pulse, the three sections, the first section of 2000Hz pulse frequency, pulse number of 2000; the second segment pulse frequency of 4000Hz, the pulse number of 4000; the third paragraph of the pulse frequency is 6000Hz, number of pulses is 6000, no wait condition.

612

613

(% class="table-bordered" %)

614

615

|1|2000|2000|No waiting condition|K0

616

|2|4000|4000|No waiting condition|K0

617

|3|6000|6000|No waiting condition|K0

618

619

PLC ladder setting as below:

620

621

(% style="text-align:center" %)

622

[[image:1620463660756-329.png||height="914" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

627

[[image:1620463666488-698.png||height="217" width="400" class="img-thumbnail"]]

b) Wait time

S,,1,, + 14 + 10 * N (word) = 1, the waiting time. S,,1,, + 15 + 10 * N (word) = 0, D is waiting registers, wait = 1 is constant.

632

633

After the completion of the current segment pulse output start time, when the timer time in place, immediately jump to a specified pulse period; measured time may be a constant or a register designated D, Unit: ms (range 1-65535ms).

634

635

**Example: **current pulse, the three sections, the first stage pulse frequency is 2000Hz, number of pulses is 2000, the waiting time K100 (Unit: MS); second stage pulse frequency of 4000Hz, the number of 4000 pulses, DlOO waiting time; first three sections pulse frequency of 6000Hz, number of pulses is 6000, no wait condition.

636

637

(% class="table-bordered" %)

638

639

|1|2000|2000|Waiting time|K100

640

|2|4000|4000|Waiting time|D100

641

|3|6000|6000|No waiting condition|K0

642

643

PLC ladder setting as below:

644

645

(% style="text-align:center" %)

646

[[image:1620463673319-877.png||height="1162" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

651

[[image:1620463679793-871.png||height="324" width="500" class="img-thumbnail"]]

c) Wait signal:

S,,1,,+ 14 + 10 * N (word) = 2 is waiting for a signal. S,,1,, + 15 + 10 * N (word) = 0, the wait signal X, M = 1 is waiting for a signal.

656

657

After the completion of the current transmission burst, begins waiting 'waiting condition "in the signal, when the signal is ON, the transmission of the next burst starts. Signal can be X, M-bit registers.

658

659

**Example:** current pulse, the three sections, the first stage pulse frequency is 2000Hz, number of pulses is 2000, waiting for the signal to M2; second stage pulse frequency of 4000Hz, number of pulses is 4000, the wait signal is an X2; third segment pulse frequency of 6000Hz, number of pulses is 6000, no wait condition.

660

661

(% class="table-bordered" %)

662

663

|1|2000|2000|Waiting for the signal|M2

664

|2|4000|4000|Waiting for the signal|X2

665

|3|6000|6000|No waiting condition|K0

666

667

PLC ladder setting as below:

668

669

(% style="text-align:center" %)

670

[[image:1620463689627-462.png||height="1344" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

675

[[image:1620463696399-746.png||height="443" width="500" class="img-thumbnail"]]

676

677

If the signal is received before sending the next segment immediately after the end of the current period.

678

679

Pulse waveform is as follows:

680

681

(% style="text-align:center" %)

682

[[image:1620463701461-694.png||height="396" width="400" class="img-thumbnail"]]

d) Trigger signal:

S,,1,, + 14 + 10 * N (word) = 3 when a trigger signal. S,,1,, + 15 + 10 * N (word) = 0 when the trigger signal X, M = 1 when the trigger signal.

687

688

After the burst transmission start pulse current, if the current number of pulses before transmitting end, the outer portion of the trigger signal operation (ON state), the pulse immediately transmits the next segment. At the end of the current pulse is sent segment, if no trigger signal (OFF state), it will continue to send the next segment pulse (i.e., pulse period will be configured represents a no-wait mode pulsing conditions, but pulse current segment transmission a trigger signal received during will directly deceleration pulse to the next paragraph).

689

690

**Example:** current pulse, the three sections, the first stage pulse frequency is 2000Hz, number of pulses is 2000, the trigger signal is M2; second stage pulse frequency of 4000Hz, number of pulses is 4000, an X2 is a trigger signal; a third segment pulse frequency of 6000Hz, number of pulses is 6000, no wait condition.

691

692

(% class="table-bordered" %)

693

694

|1|2000|2000|Waiting for the signal|M2

695

|2|4000|4000|Waiting for the signal|X2

696

|3|6000|6000|No waiting condition|K0

697

698

PLC ladder setting as below:

699

700

(% style="text-align:center" %)

701

[[image:1620463723045-420.png||height="1142" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

706

[[image:1620463718288-804.png||height="382" width="400" class="img-thumbnail"]]

707

708

If the received signal in the received signal in advance or the acceleration section, the acceleration in the current segment to the next segment pulse frequency directly.

Pulse waveform:

(% style="text-align:center" %)

713

[[image:1620463722095-402.png||height="379" width="400" class="img-thumbnail"]]

714

715

**✎Note: **in response to a trigger signal to trigger interrupt.

716

717

(6) The number of pulses is not enough to accelerate to the instruction frequency

718

719

a) Single-stage pulse:

720

721

If the number of pulses is not enough to accelerate to the instruction frequency, pulse waveform is triangular.

722

723

(% class="table-bordered" %)

724

725

|1|6000|400|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

730

[[image:1620463729305-104.png||height="295" width="300" class="img-thumbnail"]]

b) Multi-pulse:

Before the addition mode, the number of the current segment if the pulse is transmitted, the pulse frequency setting section does not reach the frequency, the pulse frequency "hop" occurs, i.e. a direct jump to the next section of the frequency.

735

736

(% class="table-bordered" %)

737

738

|1|2000|200|No waiting condition|K0

739

|2|4000|4000|No waiting condition|K0

740

|3|6000|6000|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

745

[[image:1620463734909-385.png||height="248" width="400" class="img-thumbnail"]]

746

747

After the addition mode, the number of the current segment if the pulse transmission is completed, the pulse frequency does not reach the set frequency segment, it will continue at the current frequency of the transmission pulse period, up until the end of transmission of the pulse.

748

749

(% class="table-bordered" %)

750

751

|1|2000|200|No waiting condition|K0

752

|2|4000|4000|No waiting condition|K0

753

|3|6000|200|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

758

[[image:1620463760934-382.png||height="308" width="300" class="img-thumbnail"]]

759

760

**✎Note: **

761

1) During the execution of instructions, even changing the contents of the operation cannot be manifested in the current run, the only effective when the next instruction is executed.

762

763

2) If during instruction execution, the instruction driven contacts becomes OFF, and the deceleration stop completion flag M8029 performed at this time does not operate;

764

765

3) Positioning instruction (ZRN / PLSV / DRVI / DRVA / PLSR2) may be used more than once in the program, but not to the same output port at the same time the output operations.

766

767

4) When the trigger current of the instruction is OFF, when it is triggered again, it must be after the operation bit (Y000:[M8147]; Y001:[M8148]; Y002:[M8149]; Y003:[M8150]) , can trigger again.

768

769

5) When the positioning instruction is triggered again, it must have an OFF time of one cycle or more. If the re-trigger is executed within a shorter time than the above conditions, [Operation Error] will occur when the first instruction is executed (calculated).

770

771

6) A sufficient number of pulses set for acceleration and deceleration.

772

773

= **6.8.12 PTO instruction** =

774

775

**Instruction description**

776

777

(% class="table-bordered" %)

778

779

|PTO|(% rowspan="2" %)Pulse envelope output instruction|16|No|(% rowspan="2" %)PTO S,,1,, S,,2,,|5

780

|DPTO|32|No|9

781

782

(% class="table-bordered" %)

783

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

784

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

785

|S,,1,,| | | | | | | | | | | | | |√| |

786

|S,,2,,| |√| | | | | | | | | | | | | |

787

788

Take operator S1 as the starting address, then the data table is as below:

789

790

(% class="table-bordered" %)

791

|**ADDRESS OFFSET**|**SECTION**|**DESCRIPTION**

792

|0|(% rowspan="4" %) |Number of segments: 1 to 255 (0 means no output)

793

|1|Record the number currently being

794

|2|(((

795

The number of executions of the Envelope table (-1: doesn’t execute

796

797

0: always execute ) ( Restart to take effect)

798

)))

799

|.....|Reserved

800

|10|(% rowspan="3" %)#1|Initial frequency (range of frequencies) (0~~200,000)

801

|11|Frequency increment (signed: -20,000~~20,000)

802

|12|Pulse number(1-4,294,967,295)

803

|13|(% rowspan="3" %)#2|Initial frequency(range of frequencies) (0~~200,000)

804

|14|Frequency increment (signed: -20,000~~20,000)

805

|15|Pulse number (1-4,294,967,295)

806

|(continuous)|#3|(continuous)

807

808

When using the 32-bit instruction DPTO, the address offset is 2.

**Program example**

(% style="text-align:center" %)

813

[[image:7-7 High speed process_html_dcb9a63e226337ca.jpg||height="64" width="300" class="img-thumbnail"]]

814

815

Use the PTO to control a stepper motor to achieve a simple acceleration, constant speed and deceleration or a complex process consisting of up to 255 pulses, and every waveform is acceleration, constant speed or deceleration operation. Starting and final pulse frequency is 2KHZ, the maximum pulse frequency is 10KHZ, and it requires 4000 pulses to achieve the desired number of revolutions of the motor.

816

817

(% style="text-align:center" %)

818

[[image:7-7 High speed process_html_223ae1db241e8916.jpg||height="295" width="600" class="img-thumbnail"]]

819

820

The example above required to produce a output signal contained three sections:

821

822

* Acceleration (section 1);

823

* Constant speed (section 2);

824

* Deceleration (section 3);

825

826

Frequency increment of each section:

827

828

* Sec 1(acceleration) frequency increment=40

829

* Sec 2(constant speed) frequency increment=0

830

* Sec 3(deceleration) frequency increment= -20

831

832

The corresponding envelope table is as below:

833

834

(% class="table-bordered" %)

835

|**Segment**|**Register address**|**Value**|**Description**

836

|(% rowspan="3" %)Parameter setting|D0|3|Total segments

837

|D1|0|Record the number currently being executed

838

|D2|0|Number of executions of envelope table

839

|(% rowspan="3" %)#1|D10|2khz|Initial frequency

840

|D11|40|Frequency increment

841

|D12|200|Pulse number

842

|(% rowspan="3" %)#2|D13|10khz|Initial frequency

843

|D14|0|Frequency increment

844

|D15|3400|Pulse number

845

|(% rowspan="3" %)#3|D16|10khz|Initial frequency

846

|D17|-20|Frequency increment

847

|D18|400|Pulse number

**Note for use:**

1. Take the frequency as the standard, run the command during the operation.

852

1. The range of frequency:0 to 100 kHz

853

1. If the envelope table is beyond the effective range of the device, no pulse will be sent out.

854

1. Frequency increment formula:

855

1. Frequency increment= (final frequency - initial frequency)/ the number of pulse

856

1. The frequency interval of pulse (including inter-segment and segment) couldnot exceed 2000Hz, otherwise it will go wrong (the wrong number is 6780) and the instruction will not be executed.

857

1. If the frequency interval of pulse (including inter-segment and segment) exceeds 2000Hz, then PTO will not be executed:

858

859

* Cyclic transmission mode: the last pulse of the last segment and the first pulse of the first segment are regarded as the neighboring pulse.

860

* Single transmission mode: the last pulse of the last segment and the first pulse of the first segment are not regarded as the neighboring pulse.

Wiki source code of 08 High speed process

Navigation

Table of Contents