08 High speed process

Standard PLC operation processes output and input status between the END instruction of one program scould and step 0 of the following program scould. If an immediate update of the I/O device status is required, the REF instruction is used.

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REF could be used between the instruction FOR~~ NEXT or CJ.

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REF could be used in the interrupt subprogram to refresh the input information and the output result.

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The delay of the input port state depends on the filter time of the input device. X0 to X7 have the digital filter function, the filter time is between 0 and 60 ms, the other IO ports are hardware filter that the filter time is 10 ms. The specific parameter you need to refer to the PLC manual.

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The delay of the output port state change depends on the response time of the output element, such as relay. The output contact will not act until the response time of the relay or transistor is over.

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The response latency of the relay output type plc is about 10 ms (max :20ms),the high speed output port of the transistor plc is about 10 us, for the common output port of the transistor plc is about 0.5 ms. The specific parameter you need to refer to the PLC manual.

**Program example**

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[[image:7-7 High speed process_html_db0844dad4d33f1.jpg||height="65" width="300" class="img-thumbnail"]]

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During the operation, once X20 is ON, the state of the input port X0 to X17 will be read immediately, the input signal will be refreshed and there is no input delay.

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[[image:7-7 High speed process_html_f11c740cefc73df8.jpg||height="66" width="300" class="img-thumbnail"]]

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During the operation, once X20 is ON, the state of the output port Y0 to Y17 will be read immediately, the output signal will be refreshed immediately rather than until the END instruction.

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= **6.8.2 REFF instruction** =

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**Instruction description**

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|REFF|(% rowspan="2" %)Inputs are refreshed, and their input filters are reset to the newly designated value|16|No|(% rowspan="2" %)REFF n|7

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|REFFP|16|No|7

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n is the filter time for X0 ~~ X7 input port.

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X0~~X7 use digital filters, the default filter time is set by the D8020. D8020 could be changed to 0 ~~ 60ms by REFF instruction. The remaining X ports only have hardware RC filter that the filter time is about 10ms and couldn’t be changed.

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When using the interrupts or high speed counting, the filter time of the related port reduce to minimum automatically. The unrelated ports stay as it was.

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User could also use MOV instruction to change the value of D8020.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|n|(% colspan="16" %)Constant, n=0~~60, the unit is ms

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| | | | | | | | | | | | | | | | |

**Program example**

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[[image:7-7 High speed process_html_bcb03d347f659e21.jpg||height="237" width="300" class="img-thumbnail"]]

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When X10 is triggered, the filter time of X0~~X7 is 5ms, when X10 is OFF, The filter time of X0~~ X7 is 15 ms.

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= **6.8.3 MTR instruction** =

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**Instruction description**

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|MTR|Multiplexes a bank of inputs into a number of sets of devices. Could only be used once.|16|No|MTR S D,,1,, D,,2,, n|9

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This instruction is only for transistor plc. This instruction allows a selection of 8 consecutive input devices (head address S) to be used multiple times, i.e. each physical input has more than one, separate and quite different (D,,1,,) signal being processed. The result is stored in a matrix-table (head address D,,2,,). “n” is the number of scouldning column in matrix.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S|√| | | | | | | | | | | | | | |

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|D1| |√| | | | | | | | | | | | | |

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|D2| |√|√|√| | | | | | | | | | | |

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|n|(% colspan="16" %)Constant, n=2~~8

**Program example**

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[[image:7-7 High speed process_html_ec8c75f5060253a5.jpg||height="54" width="400" class="img-thumbnail"]]

**The wiring:**

When output Y30 is ON only those inputs in the first bank are read. These results are then stored; in this example, auxiliary coils M10 to M17. The second step involves Y30 going OFF and Y31coming ON. This time only inputs in the second bank are read. These results are stored in devices M20 to M27. The last step of this example has Y31 going OFF and Y32 coming ON. This then allows all of the inputs in the second bank to be read and stored in devices M20 to M27. The processing of this instruction example would take 20 × 2 = 40 msec.

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A scouldning input with a maximum of 64 points could be achieved using 8-point X output and 8-point transistor Y output. But it is not suitable for high speed input operations because it needs a time of 20 ms,8 line= 160 ms to read each input. Therefore, the ports after X20 are typically used as the scouldning inputs. This instruction is allowed to be used only once in the program.

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[[image:7-7 High speed process_html_d712c907a19ec1b6.jpg||height="458" width="600" class="img-thumbnail"]]

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= **6.8.4 DHSCR instruction** =

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**Instruction description**

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|DHSCR|Resets the selected output when the specified high speed counter equals the test value|32|No|DHSCR S,,1,, S,,2,, D|13

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The HSCR compares the current value of the selected high speed counter (S,,2,,) against a selected value (S,,1,,). When the counters current value changes to a value equal to S1, the device specified as the destination (D) is reset.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S,,2,,| | | | | | | | | | | | |√| | |

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|D| |√|√|√| | | | | | | | | | | |

**Program example**

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[[image:7-7 High speed process_html_d4622aff42a2be76.jpg||height="157" width="600" class="img-thumbnail"]]

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In the example above, Y10 would be reset only when C255’s value stepped from 199 to 200 or from 201 to 200. If the current value of C255 was forced to equal 200 by test techniques, output Y10 would NOT reset.

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The operation principle of the HSCR command is similar to that of the HSCS instruction, except that the HSCR output action is just opposite to the HSCS instruction, i.e., when the counter value is equal, the specified output will be reset.

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**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time.

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= **6.8.5 DHSCS instruction** =

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**Instruction description**

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|DHSCS|Sets the selected output when the specified high speed counter value equals the test value|32|No|DHSCS S,,1,, S,,2,, D|13

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The HSCS set, compares the current value of the selected high speed counter (S,,2,,) against a selected value (S,,1,,). When the counters current value changes to a value equal to S1 the device specified as the destination (D) is set ON.

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It is recommended that the drive input used for the high speed counter functions; HSCS, HSCR, HSCZ is the special auxiliary RUN contact M8000.

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If more than one high speed counters function is used for a single counter the selected flag devices (D) should be kept within 1 group of 8 devices, i.e. Y0-7, M10-17.

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All high speed counter functions use an interrupt process; hence, all destination devices (D) are updated immediately.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S,,2,,| | | | | | | | | | | | |√| | |

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|D| |√|√|√| | | | | | | | | | | |

**Program example**

**Example 1:**

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[[image:7-7 High speed process_html_3aace41414766cc2.jpg||height="156" width="600" class="img-thumbnail"]]

**Example 2:**

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[[image:7-7 High speed process_html_89438e3da1774961.jpg||height="193" width="300" class="img-thumbnail"]]

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LX3V could use interrupt pointers I010 through I060 (6 points) as destination devices (D). This enables interrupt routines to be triggered directly when the value of the specified high speed counter reaches the value in the HSCS instruction. When (D) is between I010~~I060, the subprogram for interrupting 0~~5 in the high-speed counter needs to be initiated.

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**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time.

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= **6.8.6 DHSZ instruction** =

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**Instruction description**

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|DHSZ|The current value of a high speed counter is checked against a specified range|32|No|DHSZ S,,1,, S,,2,, S D|17

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This instruction works in exactly the same way as the standard ZCP. The only difference is that the device being compared is a high speed counter (specified as S). Also, all of the outputs (D) are updated immediately due to the interrupt operation of the DHSZ. It should be remembered that when a device is specified in operand D it is in fact a head address for 3 consecutive devices. Each one is used to represent the status of the current comparison.

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* S,,1,, is the lower limit; S,,1,, must be equal to or less than S2.

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* S,,2,, is the upper limit.

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* S must be C235~~C255, because C235~~C255 are 32bit counter, so user must use DHSZ not HSZ.

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* D is for storing comparison result. When it is Y0~~Y17 or M or S, there is no latency. For other output port, the output will not be executed until program END.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S| | | | | | | | | | | | |√| | |

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|D| |√|√|√| | | | | | | | | | | |

**Program example**

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[[image:7-7 High speed process_html_5a7b133dc73dd30f.jpg||height="224" width="500" class="img-thumbnail"]]

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**Note: **There is no limit on the number of DHSZ,DHSCS and DHSCR created, but only 6 DHSZ, DHSCS, and DHSCR can be active at the same time.

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**Instruction description**

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|SPD|Detects the number of ‘encoder’ pulses in a given time frame. Results could be used to calculate speed|16|No|SPD S,,1,, S,,2,, D|7

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The number of pulses received at S,,1,, are counted and stored in D+1; this is the current count value. The counting takes place over a set time frame specified by S,,2,, in msec. The time remaining on the current ‘timed count’, is displayed in device D+2.

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The number of counted pulses (of S,,1,,) from the last timed count is stored in D.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S,,1,,|√| | | | | | | | | | | | | | |

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|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|D| | | | | | | | | | | |√|√|√|√|√

**Program example**

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[[image:7-7 High speed process_html_82860708e693606a.jpg||height="77" width="400" class="img-thumbnail"]]

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X0 is the pulse input port.

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D0 defines the set time frame.

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Current count value, device D10

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Accumulated/ last count value, device D11

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Current time remaining in msec, device D12

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= **6.8.8 PLSY instruction** =

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**Instruction description**

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|PLSY|(% rowspan="2" %)Outputs a specified number of pulses at a set frequency|16|No|(% rowspan="2" %)PLSY S,,1,, S,,2,, D|7

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|DPLSY|32|Yes|13

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A specified quantity (S2) of pulses is output through device D at a specified frequency S1. This instruction is used in situations where the quantity of outputs is of primary concern.

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For PLSY, S1’s range is 1~~32767 Hz, for DPLSY, S1’s range is 1~~200000 Hz.

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For PLSY, S2’s range is 1~~32767, for DPLSY, S1’s range is 1~~2147483647. If S2 is 0, it means there is no limitation for the output pulse quantity.

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For LX3V/3VP/3VE, D could be Y0~~Y3. For LX3V (1s) type, D could only be Y0 or Y1.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S,,1,,| | | | | | | |√|√|√|√|√|√|√|√|√

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|S,,2,,| | | | | | | |√|√|√|√|√|√|√|√|√

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|D| |√| | | | | | | | | | | | | |

**Program example**

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[[image:7-7 High speed process_html_96c6d839f94ba458.jpg||height="61" width="400" class="img-thumbnail"]]

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In the example, when X0 is OFF, the output becomes 0 too, when X0 becomes ON again it will react initially.

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A single pulse is described as having a 50% duty cycle. This means it is ON for 50% of the pulse and OFF for the 50% of the pulse. The actual is controlled by interrupt handling, i.e. the output cycle is not affected by the scould time of the program.

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The pulse completion flag (M8029) is set when the PLSY instruction is done.

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**The related variable in the PLSY:**

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* D8141 (high byte), D8140 (low byte): Y000 the count of output pulse, when the direction is reverse, Y000 decrease. (32-bits)

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* D8143 (high byte), D8142 (low byte): Y001 the count of output pulse, when the direction is reverse, Y000 decrease. (32-bits)

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* D8151 (high byte), D8150 (low byte): Y002 the count of output pulse, when the direction is reverse, Y000 decrease.(32-bit)

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* D8153 (high byte), D8152 (low byte): Y003 the count of output pulse, when the direction is reverse, Y000 decrease.(32-bit)

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* M8145: Y000 stop output pulse (immediately)

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* M8146: Y001 stop output pulse (immediately)

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* M8152: Y002 stop output pulse (immediately)

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* M8153: Y003 stop output pulse (immediately)

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* M8147: Y000 monitor in the output pulse(BUSY/READY)

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* M8148: Y001 monitor in the output pulse(BUSY/READY)

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* M8149: Y002 monitor in the output pulse(BUSY/READY)

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* M8150: Y003 monitor in the output pulse(BUSY/READY)

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= **6.8.9 PWM instruction** =

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**Instruction description**

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|PWM|Generates a pulse train with defined pulse characteristics|16|No|PWM S,,1,, S,,2,, D|7

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Only transistor type PLC could support PWM instruction. S,,1,, defines the width of the pulse, S,,2,, defines the pulse period, and D defines the output port. For LX3V (1S firmware), the output port could be Y0 or Y1, for LX3V (2N firmware), the output port could be Y0~~Y3.

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The output port couldn’t be the same with PLSY or PLSR instruction.

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S,,1,, <= S,,2,,, the setting range of S,,1,, is 0~~32767 ms. S,,2,, ranges from 1 to 32767ms.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|**X**|**Y**|**M**|**S**|**K**|**H**|**E**|**KnX**|**KnY**|**KnM**|**KnS**|**T**|**C**|**D**|**V**|**Z**

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|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|D| |√| | | | | | | | | | | | | |

**Program example**

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[[image:7-7 High speed process_html_d3d534d5d0b8fb51.jpg||height="197" width="500" class="img-thumbnail"]]

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**Thousand-ratio pattern**

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The thousand-ratio pattern: the thousand-ratio pattern is to divide the periodic parameters evenly equal to 1000. The user sets correspond to the control bit ON for thousand-ratio pattern as follows:

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|**Outputs**|Y0|Y1|Y2|Y3

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|**Control bits**|M8134|M8135|M8136|M8137

**[Example]**

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[[image:7-7 High speed process_html_cef6612aa705d4ce.jpg||height="262" width="500" class="img-thumbnail"]]

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Cycle set to 100ms, duty ratio if set to 500, then output to high level is 50ms, low level is 50ms; duty ratio if set to 100, then output to high level is 10ms, low level is 90ms; duty ratio if set to 900, then output high level is 90ms, low level is 10ms;

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**Calculation formula:** t (ms) =T0 (ms) *K/1000

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High level time (ms) = cycle time (ms) * duty ratio/1000

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Low level time (ms) = cycle time (ms) – high level time (ms)

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= **6.8.10 PLSR instruction** =

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**Instruction description**

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|(% style="width:93px" %)PLSY|(% rowspan="2" style="width:535px" %)Outputs a specified number of pulses at a set frequency|16|No|(% rowspan="2" %)PLSY S,,1,, S,,2,, S,,3,, D|7

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|(% style="width:93px" %)DPLSY|32|Yes|17

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Because of the nature of the high speed output, transistor output units should be used with this instruction. Relay outputs will suffer from a greatly reduced life and will cause false outputs to occur due to the mechanical ‘bounce’ of the contacts.

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* S,,1,,: The maximum frequency, the range is 10~~100,000Hz

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* S,,2,,: A specified quantity of output pulses, 16-bit operation: 110 to 32,767 pulses, 32-bit operation: 110 to 2,147,483,647 pulses. If it was less than 110, PLC couldn’t output pulse;

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* S,,3,,: The acceleration time, the range is 10~~32,000 (ms).

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* D: output port, for LX3V/3VP/3VE, D could be Y0~~Y3, for LX3V (1s) type, D could only be Y0 or Y1.

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|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S,,1,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S,,2,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|S,,3,,| | | | |√|√| |√|√|√|√|√|√|√|√|√

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|D| |√| | | | | | | | | | | | | |

**Program example**

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[[image:7-7 High speed process_html_3b46454b18532a23.jpg||height="103" width="500" class="img-thumbnail"]]

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[[image:7-7 High speed process_html_1f699763d7829b6.jpg||height="310" width="700" class="img-thumbnail"]]

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The special registers corresponding to each output port are listed as follow:

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|(% colspan="2" style="width:149px" %)**Register**|(% style="width:523px" %)**Definition**|**Remarks**

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|D8140|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y0 port set in the PLSY or PLSR instruction|(% rowspan="10" %)Applicable instructions: use DMOV K0 D81xx to perform clear operation

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|D8140|(% style="width:91px" %)High byte

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|D8142|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y1 port set in the PLSY or PLSR instruction

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|D8143|(% style="width:91px" %)High byte

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|D8150|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y2 port set in the PLSY or PLSR instruction

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|D8151|(% style="width:91px" %)High byte

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|D8152|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Number of total pulses output to Y3 port set in the PLSY or PLSR instruction

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|D8153|(% style="width:91px" %)High byte

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|D8136|(% style="width:91px" %)Low byte|(% rowspan="2" style="width:523px" %)Accumulative value of the number of the pulses already output to Y0 and Y1

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|D8137|(% style="width:91px" %)High byte

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The output frequency range of this instruction is 10 ~~ 100, 000Hz. When it is out of range, it will be automatically converted into the range and then executed. However, the actual output frequency depends on the following formula.

Output frequency=

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[[image:7-7 High speed process_html_264371750fbe73ba.jpg||height="27" width="400" class="img-thumbnail"]]

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The frequency of the initial and final stages of acceleration should not be lower than the result of the above formula.

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Example: Maximum speed is 50,000, acceleration /deceleration time is 100ms.

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[[image:7-7 High speed process_html_19453a8b227b5316.jpg]] = 500 (Hz)

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When maximum frequency S1 is specified to 50000Hz, the actual output frequency at the early stage of acceleration and at the late stage of deceleration is 500Hz.

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[[image:7-7 High speed process_html_5692a599dd293f8a.jpg||height="242" width="600" class="img-thumbnail"]]

1. **Note for use**

* The instruction is executed in an interruption way; therefore, it will not be influenced by the scouldning cycle;

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* When the instruction power flow is OFF, the deceleration stop is active; when the power flow is changed from OFF→ON, the pulse output process starts over again.

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* During the pulse output process, changing the operand has no effect on this output, and the modified content will take effect when the instruction is executed next time.

412

* Special auxiliary coil M8029 is turned ON when the specified number of pulses has been completed. The pulse count and completion flag (M8029) are reset when the PLSY instruction is de-energized. If “0" (zero) is specified, the PLSY instruction will continue generating pulses for as long as the instruction is energized.

413

* The process couldn’t be repeated with the output port number of the PWM instruction.

414

415

= **6.8.11 PLSR2 instruction** =

416

417

**1) Instruction description**

418

419

(% class="table-bordered" %)

420

421

|PLSR2|Multi-speed pulse output|16|No |PLSR2 S,,1,,D,,1,,D,,2,,|7

422

423

(% class="table-bordered" %)

424

|(% rowspan="2" %)**Operand** |(% colspan="4" %)**Bit device **|(% colspan="12" %)**Word device**

425

|X|Y|M|S|K|H |E|KnX|KnY|KnM |KnS|T |C|D|V|Z

426

|S ,,1,,| | | | | | | | | | | | | |v| |

427

|D,,1,,| |v| | | | | | | | | | | | | |

428

|D,,2,,| |v|v|v| | | | | | | | | | | |

429

430

This instruction is only valid for LX3VP series PLC.

431

432

PLSR2 instruction sets parameters on table list, and generates relative/ absolute position pulse according specified port, frequency, direction and ramp time. so that servo actuator gives the offset on the motion based on the current position. Only transistor output PLC supports this instruction.

433

434

S,,1,,: Register parameter, Dn is the start register of the specified register segment;

435

436

D,,1,, Pulse output port, designated Y0-Y3;

437

438

D,,2,,: The direction or position variable output port, ON: indicates the operating forward; otherwise, run in reverse.

439

440

441

(% style="text-align:center" %)

442

[[image:1620463452720-887.png||height="77" width="400" class="img-thumbnail"]]

443

444

445

(% class="table-bordered" %)

|(((

**S,,1,,**

**Register offset**

)))|**Content**|**Description**

451

|S,,1,,+0|Table flag|Retention

452

|S,,1,,+1|Table version|Retention

453

|S,,1,,+2|Pulse total number of segments|1-12

454

|S,,1,,+3|Acceleration and deceleration mode|0: First acceleration mode; 1: Later acceleration mode

455

|S,,1,,+4|Acceleration time|50-32000ms

456

|S,,1,,+5|Deceleration time|50-32000ms

457

|S,,1,,+6|Default frequency|10HZ-200KHZ

458

|S,,1,,+7| |

459

|S,,1,,+8|Relative / absolute mode|0: relative; 1: Absolute

460

|S,,1,,+ 9-** **S,,1,,+19|Retention|Retention

461

|S,,1,,+20|First segment pulse frequency|10HZ-200KHZ

462

|S,,1,,+21| |

463

|S,,1,,+22|First segment total number of pulses|No

464

|S,,1,,+23| |

465

|S,,1,,+24|First segment wait condition|(((

466

0: pulse transmission is completed;

1: waiting time;

2: wait signal;

3: Trigger signal. (With [waiting condition] and [Pending Register] with use)

473

)))

474

|S,,1,,+25|First segment Wait register type|(((

475

Waiting condition register type and relationship:

476

477

Pulse transmission completion: None

478

479

Waiting time: = 0: D register; = 1: constant;

480

481

Wait signal: = 0: X register; = 1: M bit register;

482

483

Trigger: = 0: X register; = 1: M bit register.

484

)))

485

|S,,1,,+26|First segment constant value / standby register number|No

486

|S,,1,,+27| |

487

|S,,1,,+28|Retention|Retention

488

|S,,1,,+29|Retention|Retention

489

|...|...|...

490

|S,,1,,+ 10 + n * 10|The N-th pulse frequency|10HZ - 200KHZ

491

492

**2) Programming example**

493

494

The demonstration shown below is parameters settings for 4 segments pulse starting with D0, the acceleration time is 100 ms from lowest frequency to the default frequency(100,000Hz), the deceleration time is 100 ms, it is in absolute mode.

495

496

497

(% style="text-align:center" %)

498

[[image:1620463472811-235.png||height="374" width="700" class="img-thumbnail"]]

499

500

The number of pulses of the frequency of each segment and the wait condition as follows:

501

502

(% class="table-bordered" %)

503

504

|1|10,000|10,000|waiting time|K100

505

|2|20,000|20,000|Waiting for the signal|M1

506

|3|15,000|40,000|Trigger|X1

507

|4|30,000|60,000|No wait condition|K0

508

509

Configured in accordance with parameters:

510

511

(% style="text-align:center" %)

512

[[image:1620463489594-301.png||height="1128" width="700" class="img-thumbnail"]]

513

514

**3) Parameter Description**

515

516

1) ** **S,,1,,+2: pulse for setting the number of stages (word), a data range 1-12, it means support 1-12 segments;

517

518

2) Acceleration and deceleration modes

519

520

S,,1,,+3: to set the acceleration and deceleration patterns (words), is set to 0 before the addition mode is set to 1 after addition mode, wherein:

521

522

a) Early acceleration mode: When a multi-stage pulse is applied and the first stage pulse finished according to first stage frequency, the next stage frequency has been accelerated in advance.

523

524

b) Later acceleration mode: When a multi-stage pulse is applied and the first stage pulse finished according to first stage frequency, the next stage frequency just begin to accelerate.

525

526

For example, now need three stages of pulse, the first pulse frequency is 2000Hz, the number of pulse is 2000, the second pulse frequency is 4000Hz, the number of pulse is 4000, and the third pulse frequency is 6000Hz, the number of pulse is 6000.

527

528

**Early acceleration mode as below:**

529

530

(% style="text-align:center" %)

531

[[image:1620463500954-987.png||height="305" width="500" class="img-thumbnail"]]

532

533

**Later acceleration mode as below:**

534

535

(% style="text-align:center" %)

536

[[image:1620463504313-304.png||height="303" width="500" class="img-thumbnail"]]

537

538

(3) Acceleration time, deceleration time and default frequency

539

540

S,,1,,+14 (single word) is the acceleration time;

541

542

S,,1,,+5 (single word) deceleration time;

543

544

S,,1,,+6 (double word) default frequency;

545

546

The output frequency range of this instruction is 10 ~~ 200, 000Hz. When the maximum speed(acceleration and deceleration) beyond this range,PLC will automatically convert (up or down) to the able range and perform.

547

548

The acceleration time refers to the time from the base frequency to the default frequency, and the deceleration time refers to the time from the default frequency to the base frequency.

549

550

551

(% style="text-align:center" %)

552

[[image:1620463515599-686.png||height="509" width="700" class="img-thumbnail"]]

553

554

(4) Relative, absolute mode

555

556

S1+8 (single word) is used in setting the parameters of pulse configuration for relative mode or absolute mode. When it is set to (relative mode), that means the pulse number and current value register is relative position. Set to 1 (absolute mode), that means pulse number and current value register is absolute position.

557

558

The corresponding relationship between the output port and the current pulse value register is as follows:

559

560

l [Y000] output, the current pulse value register is [D8141 (high byte), D8140 (low byte)] (32 bits)

561

562

l [Y001] output, the current pulse value register is [D8143 (high bytes), D8142 (low bytes)] (32 bits)

563

564

l [Y002] output, the current pulse value register is [D8151 (high bytes), D8150 (low bytes)] (32 bits)

565

566

l [Y003] output, the current pulse value register is [D8153 (high bytes), D8152 (low bytes)] (32 bits)

**For example**

Now need three stages of pulse, the first pulse frequency is 2000Hz, the number of pulse is 2000, the second pulse frequency is 4000Hz, the number of pulse is 4000, and the third pulse frequency is 6000Hz, the number of pulse is 6000Hz.

571

572

The corresponding mode settings are as follows:

573

574

(% class="table-bordered" %)

575

576

|1|2000|2000|No waiting condition|K0

577

|2|4000|4000|No waiting condition|K0

578

|3|6000|6000|No waiting condition|K0

579

580

PLC ladder setting as below:

581

582

(% style="text-align:center" %)

583

[[image:1620463634015-908.png||height="927" width="700" class="img-thumbnail"]]

584

585

Absolute mode setting as below:

586

587

(% class="table-bordered" %)

588

589

|1|2000|2000|No waiting condition|K0

590

|2|4000|4000|No waiting condition|K0

591

|3|6000|6000|No waiting condition|K0

592

593

PLC ladder setting as below:

594

595

(% style="text-align:center" %)

596

[[image:1620463530261-493.png||height="927" width="700" class="img-thumbnail"]]

597

598

**✎Note: **absolute mode, if the current position of the same segment with the next paragraph, it is considered the next paragraph does not exist, at some speed will drop to zero.

599

600

The following table shows the absolute mode, the first segment a second segment of the same pulse position where:

601

602

(% class="table-bordered" %)

603

604

|1|2000|2000|No waiting condition|K0

605

|2|3000|2000|No waiting condition|K0

606

|3|2000|3000|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

612

[[image:1620463650482-502.png||height="224" width="300" class="img-thumbnail"]]

(5) Wait condition

S,,1,,+ 14 + 10 * N (word) is the wait condition paragraph N, S,,1,,+ 15 + 10 * N (word) register type waiting, S,,1,,+ 16 + 10 * N (double word) waiting ID register / constant value. Wait condition = 0 is no wait condition, when latency = 1, 2 = wait for signals, the trigger signal = 3.

617

618

Wait condition and waiting and waiting for the register number register / constant value used in conjunction.

619

620

a) No wait condition:

621

622

S,,1,,+ 14 + 10 * N (word) = 0 is no wait condition. After performing the set pulse number of this paragraph, immediately jump to a specified later burst.

623

624

**Example: **current pulse, the three sections, the first section of 2000Hz pulse frequency, pulse number of 2000; the second segment pulse frequency of 4000Hz, the pulse number of 4000; the third paragraph of the pulse frequency is 6000Hz, number of pulses is 6000, no wait condition.

625

626

(% class="table-bordered" %)

627

628

|1|2000|2000|No waiting condition|K0

629

|2|4000|4000|No waiting condition|K0

630

|3|6000|6000|No waiting condition|K0

631

632

PLC ladder setting as below:

633

634

(% style="text-align:center" %)

635

[[image:1620463660756-329.png||height="914" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

640

[[image:1620463666488-698.png||height="217" width="400" class="img-thumbnail"]]

b) Wait time

S,,1,, + 14 + 10 * N (word) = 1, the waiting time. S,,1,, + 15 + 10 * N (word) = 0, D is waiting registers, wait = 1 is constant.

645

646

After the completion of the current segment pulse output start time, when the timer time in place, immediately jump to a specified pulse period; measured time may be a constant or a register designated D, Unit: ms (range 1-65535ms).

647

648

**Example: **current pulse, the three sections, the first stage pulse frequency is 2000Hz, number of pulses is 2000, the waiting time K100 (Unit: MS); second stage pulse frequency of 4000Hz, the number of 4000 pulses, DlOO waiting time; first three sections pulse frequency of 6000Hz, number of pulses is 6000, no wait condition.

649

650

(% class="table-bordered" %)

651

652

|1|2000|2000|Waiting time|K100

653

|2|4000|4000|Waiting time|D100

654

|3|6000|6000|No waiting condition|K0

655

656

PLC ladder setting as below:

657

658

(% style="text-align:center" %)

659

[[image:1620463673319-877.png||height="1162" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

664

[[image:1620463679793-871.png||height="324" width="500" class="img-thumbnail"]]

c) Wait signal:

S,,1,,+ 14 + 10 * N (word) = 2 is waiting for a signal. S,,1,, + 15 + 10 * N (word) = 0, the wait signal X, M = 1 is waiting for a signal.

669

670

After the completion of the current transmission burst, begins waiting 'waiting condition "in the signal, when the signal is ON, the transmission of the next burst starts. Signal can be X, M-bit registers.

671

672

**Example:** current pulse, the three sections, the first stage pulse frequency is 2000Hz, number of pulses is 2000, waiting for the signal to M2; second stage pulse frequency of 4000Hz, number of pulses is 4000, the wait signal is an X2; third segment pulse frequency of 6000Hz, number of pulses is 6000, no wait condition.

673

674

(% class="table-bordered" %)

675

676

|1|2000|2000|Waiting for the signal|M2

677

|2|4000|4000|Waiting for the signal|X2

678

|3|6000|6000|No waiting condition|K0

679

680

PLC ladder setting as below:

681

682

(% style="text-align:center" %)

683

[[image:1620463689627-462.png||height="1344" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

688

[[image:1620463696399-746.png||height="443" width="500" class="img-thumbnail"]]

689

690

If the signal is received before sending the next segment immediately after the end of the current period.

691

692

Pulse waveform is as follows:

693

694

(% style="text-align:center" %)

695

[[image:1620463701461-694.png||height="396" width="400" class="img-thumbnail"]]

d) Trigger signal:

S,,1,, + 14 + 10 * N (word) = 3 when a trigger signal. S,,1,, + 15 + 10 * N (word) = 0 when the trigger signal X, M = 1 when the trigger signal.

700

701

After the burst transmission start pulse current, if the current number of pulses before transmitting end, the outer portion of the trigger signal operation (ON state), the pulse immediately transmits the next segment. At the end of the current pulse is sent segment, if no trigger signal (OFF state), it will continue to send the next segment pulse (i.e., pulse period will be configured represents a no-wait mode pulsing conditions, but pulse current segment transmission a trigger signal received during will directly deceleration pulse to the next paragraph).

702

703

**Example:** current pulse, the three sections, the first stage pulse frequency is 2000Hz, number of pulses is 2000, the trigger signal is M2; second stage pulse frequency of 4000Hz, number of pulses is 4000, an X2 is a trigger signal; a third segment pulse frequency of 6000Hz, number of pulses is 6000, no wait condition.

704

705

(% class="table-bordered" %)

706

707

|1|2000|2000|Waiting for the signal|M2

708

|2|4000|4000|Waiting for the signal|X2

709

|3|6000|6000|No waiting condition|K0

710

711

PLC ladder setting as below:

712

713

(% style="text-align:center" %)

714

[[image:1620463723045-420.png||height="1142" width="700" class="img-thumbnail"]]

Pulse waveform:

(% style="text-align:center" %)

719

[[image:1620463718288-804.png||height="382" width="400" class="img-thumbnail"]]

720

721

If the received signal in the received signal in advance or the acceleration section, the acceleration in the current segment to the next segment pulse frequency directly.

Pulse waveform:

(% style="text-align:center" %)

726

[[image:1620463722095-402.png||height="379" width="400" class="img-thumbnail"]]

727

728

**✎Note: **in response to a trigger signal to trigger interrupt.

729

730

(6) The number of pulses is not enough to accelerate to the instruction frequency

731

732

a) Single-stage pulse:

733

734

If the number of pulses is not enough to accelerate to the instruction frequency, pulse waveform is triangular.

735

736

(% class="table-bordered" %)

737

738

|1|6000|400|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

743

[[image:1620463729305-104.png||height="295" width="300" class="img-thumbnail"]]

b) Multi-pulse:

Before the addition mode, the number of the current segment if the pulse is transmitted, the pulse frequency setting section does not reach the frequency, the pulse frequency "hop" occurs, i.e. a direct jump to the next section of the frequency.

748

749

(% class="table-bordered" %)

750

751

|1|2000|200|No waiting condition|K0

752

|2|4000|4000|No waiting condition|K0

753

|3|6000|6000|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

758

[[image:1620463734909-385.png||height="248" width="400" class="img-thumbnail"]]

759

760

After the addition mode, the number of the current segment if the pulse transmission is completed, the pulse frequency does not reach the set frequency segment, it will continue at the current frequency of the transmission pulse period, up until the end of transmission of the pulse.

761

762

(% class="table-bordered" %)

763

764

|1|2000|200|No waiting condition|K0

765

|2|4000|4000|No waiting condition|K0

766

|3|6000|200|No waiting condition|K0

Pulse waveform:

(% style="text-align:center" %)

771

[[image:1620463760934-382.png||height="308" width="300" class="img-thumbnail"]]

772

773

**✎Note: **

774

1) During the execution of instructions, even changing the contents of the operation cannot be manifested in the current run, the only effective when the next instruction is executed.

775

776

2) If during instruction execution, the instruction driven contacts becomes OFF, and the deceleration stop completion flag M8029 performed at this time does not operate;

777

778

3) Positioning instruction (ZRN / PLSV / DRVI / DRVA / PLSR2) may be used more than once in the program, but not to the same output port at the same time the output operations.

779

780

4) When the trigger current of the instruction is OFF, when it is triggered again, it must be after the operation bit (Y000:[M8147]; Y001:[M8148]; Y002:[M8149]; Y003:[M8150]) , can trigger again.

781

782

5) When the positioning instruction is triggered again, it must have an OFF time of one cycle or more. If the re-trigger is executed within a shorter time than the above conditions, [Operation Error] will occur when the first instruction is executed (calculated).

783

784

6) A sufficient number of pulses set for acceleration and deceleration.

785

786

= **6.8.12 PTO instruction** =

787

788

**Instruction description**

789

790

(% class="table-bordered" %)

791

792

|PTO|(% rowspan="2" %)Pulse envelope output instruction|16|No|(% rowspan="2" %)PTO S,,1,, S,,2,,|5

793

|DPTO|32|No|9

794

795

(% class="table-bordered" %)

796

|(% rowspan="2" %)**Operand**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

797

|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

798

|S,,1,,| | | | | | | | | | | | | |√| |

799

|S,,2,,| |√| | | | | | | | | | | | | |

800

801

Take operator S1 as the starting address, then the data table is as below:

802

803

(% class="table-bordered" %)

804

|**ADDRESS OFFSET**|**SECTION**|**DESCRIPTION**

805

|0|(% rowspan="4" %) |Number of segments: 1 to 255 (0 means no output)

806

|1|Record the number currently being

807

|2|(((

808

The number of executions of the Envelope table (-1: doesn’t execute

809

810

0: always execute ) ( Restart to take effect)

811

)))

812

|.....|Reserved

813

|10|(% rowspan="3" %)#1|Initial frequency (range of frequencies) (0~~200,000)

814

|11|Frequency increment (signed: -20,000~~20,000)

815

|12|Pulse number(1-4,294,967,295)

816

|13|(% rowspan="3" %)#2|Initial frequency(range of frequencies) (0~~200,000)

817

|14|Frequency increment (signed: -20,000~~20,000)

818

|15|Pulse number (1-4,294,967,295)

819

|(continuous)|#3|(continuous)

820

821

When using the 32-bit instruction DPTO, the address offset is 2.

**Program example**

(% style="text-align:center" %)

826

[[image:7-7 High speed process_html_dcb9a63e226337ca.jpg||height="64" width="300" class="img-thumbnail"]]

827

828

Use the PTO to control a stepper motor to achieve a simple acceleration, constant speed and deceleration or a complex process consisting of up to 255 pulses, and every waveform is acceleration, constant speed or deceleration operation. Starting and final pulse frequency is 2KHZ, the maximum pulse frequency is 10KHZ, and it requires 4000 pulses to achieve the desired number of revolutions of the motor.

829

830

(% style="text-align:center" %)

831

[[image:7-7 High speed process_html_223ae1db241e8916.jpg||height="295" width="600" class="img-thumbnail"]]

832

833

The example above required to produce a output signal contained three sections:

834

835

* Acceleration (section 1);

836

* Constant speed (section 2);

837

* Deceleration (section 3);

838

839

Frequency increment of each section:

840

841

* Sec 1(acceleration) frequency increment=40

842

* Sec 2(constant speed) frequency increment=0

843

* Sec 3(deceleration) frequency increment= -20

844

845

The corresponding envelope table is as below:

846

847

(% class="table-bordered" %)

848

|**Segment**|**Register address**|**Value**|**Description**

849

|(% rowspan="3" %)Parameter setting|D0|3|Total segments

850

|D1|0|Record the number currently being executed

851

|D2|0|Number of executions of envelope table

852

|(% rowspan="3" %)#1|D10|2khz|Initial frequency

853

|D11|40|Frequency increment

854

|D12|200|Pulse number

855

|(% rowspan="3" %)#2|D13|10khz|Initial frequency

856

|D14|0|Frequency increment

857

|D15|3400|Pulse number

858

|(% rowspan="3" %)#3|D16|10khz|Initial frequency

859

|D17|-20|Frequency increment

860

|D18|400|Pulse number

**Note for use:**

1. Take the frequency as the standard, run the command during the operation.

865

1. The range of frequency:0 to 100 kHz

866

1. If the envelope table is beyond the effective range of the device, no pulse will be sent out.

867

1. Frequency increment formula:

868

1. Frequency increment= (final frequency - initial frequency)/ the number of pulse

869

1. The frequency interval of pulse (including inter-segment and segment) couldnot exceed 2000Hz, otherwise it will go wrong (the wrong number is 6780) and the instruction will not be executed.

870

1. If the frequency interval of pulse (including inter-segment and segment) exceeds 2000Hz, then PTO will not be executed:

871

872

* Cyclic transmission mode: the last pulse of the last segment and the first pulse of the first segment are regarded as the neighboring pulse.

873

* Single transmission mode: the last pulse of the last segment and the first pulse of the first segment are not regarded as the neighboring pulse.

Wiki source code of 08 High speed process