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Changes for page 01 Program execution

Last modified by Leo Wei on 2024/12/24 22:42
From version 13.12
edited by Stone Wu
on 2022/09/23 16:10
Change comment: (Autosaved)
To version 16.1
edited by Stone Wu
on 2022/09/23 16:31
Change comment: There is no comment for this version

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... ... @@ -361,7 +361,6 @@
361 361  * During the execution of the interrupt program, when an interrupt cause with a low priority or the same priority occurs.
362 362  ** The interruption cause that occurred is stored, and after the interrupt program in execution ends, the interrupt program corresponding to the stored interruption cause is executed. Even if the same interruption cause occurs multiple times, the interruption cause is stored only once.
363 363  
364 -
365 365  (% style="text-align:center" %)
366 366  [[image:1652249673420-476.png||class="img-thumbnail"]]
367 367  
... ... @@ -577,103 +577,103 @@
577 577  
578 578  (% class="table-bordered" %)
579 579  |=(% colspan="4" %)**External input interrupt mask register**
580 -|=**Special register number**|=**Type of interrupt**|=**Instruction**|=**Defaults**
581 -|SM352|X0 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
582 -|SM353|X0 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
583 -|SM354|X1 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
584 -|SM355|X1 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
585 -|SM356|X2 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
586 -|SM357|X2 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
587 -|SM358|X3 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
588 -|SM359|X3 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
589 -|SM360|X4 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
590 -|SM361|X4 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
591 -|SM362|X5 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
592 -|SM363|X5 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
593 -|SM364|X6 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
594 -|SM365|X6 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
595 -|SM366|X7 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
596 -|SM367|X7 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
579 +|=(% style="width: 266px;" %)**Special register number**|=(% style="width: 308px;" %)**Type of interrupt**|=(% style="width: 390px;" %)**Instruction**|=**Defaults**
580 +|(% style="width:266px" %)SM352|(% style="width:308px" %)X0 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
581 +|(% style="width:266px" %)SM353|(% style="width:308px" %)X0 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
582 +|(% style="width:266px" %)SM354|(% style="width:308px" %)X1 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
583 +|(% style="width:266px" %)SM355|(% style="width:308px" %)X1 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
584 +|(% style="width:266px" %)SM356|(% style="width:308px" %)X2 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
585 +|(% style="width:266px" %)SM357|(% style="width:308px" %)X2 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
586 +|(% style="width:266px" %)SM358|(% style="width:308px" %)X3 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
587 +|(% style="width:266px" %)SM359|(% style="width:308px" %)X3 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
588 +|(% style="width:266px" %)SM360|(% style="width:308px" %)X4 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
589 +|(% style="width:266px" %)SM361|(% style="width:308px" %)X4 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
590 +|(% style="width:266px" %)SM362|(% style="width:308px" %)X5 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
591 +|(% style="width:266px" %)SM363|(% style="width:308px" %)X5 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
592 +|(% style="width:266px" %)SM364|(% style="width:308px" %)X6 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
593 +|(% style="width:266px" %)SM365|(% style="width:308px" %)X6 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
594 +|(% style="width:266px" %)SM366|(% style="width:308px" %)X7 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
595 +|(% style="width:266px" %)SM367|(% style="width:308px" %)X7 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
597 597  
598 598  (% class="table-bordered" %)
599 -|(% colspan="4" %)**Timer interrupt mask register**
600 -|**Special register number**|**Type of interrupt**|**Instruction**|**Default**
601 -|SD350|1st to 16th timer interrupt|(((
598 +|=(% colspan="4" %)**Timer interrupt mask register**
599 +|=**Special register number**|=(% style="width: 311px;" %)**Type of interrupt**|=(% style="width: 391px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
600 +|SD350|(% style="width:311px" %)1st to 16th timer interrupt|(% style="width:391px" %)(((
602 602  Each bit can control the mask of an interrupt.
603 603  
604 -ON: Mask interrupt OFF: Enable interrupt
605 -)))|0
606 -|SD351|17th to 32th timer interrupt|(((
603 +ON: shield interrupts; OFF: interrupt allowed
604 +)))|(% style="width:110px" %)0
605 +|SD351|(% style="width:311px" %)17th to 32th timer interrupt|(% style="width:391px" %)(((
607 607  Each bit can control the mask of an interrupt.
608 608  
609 -ON: Mask interrupt OFF: Enable interrupt
610 -)))|0
611 -|SD352|33th to 48th timer interrupt|(((
608 +ON: shield interrupts; OFF: interrupt allowed
609 +)))|(% style="width:110px" %)0
610 +|SD352|(% style="width:311px" %)33th to 48th timer interrupt|(% style="width:391px" %)(((
612 612  Each bit can control the mask of an interrupt.
613 613  
614 -ON: Mask interrupt OFF: Enable interrupt
615 -)))|0
616 -|SD353|49th to 64th timer interrupt|(((
613 +ON: shield interrupts; OFF: interrupt allowed
614 +)))|(% style="width:110px" %)0
615 +|SD353|(% style="width:311px" %)49th to 64th timer interrupt|(% style="width:391px" %)(((
617 617  Each bit can control the mask of an interrupt.
618 618  
619 -ON: Mask interrupt OFF: Enable interrupt
620 -)))|0
621 -|SD354|65th to 80th timer interrupt|(((
618 +ON: shield interrupts; OFF: interrupt allowed
619 +)))|(% style="width:110px" %)0
620 +|SD354|(% style="width:311px" %)65th to 80th timer interrupt|(% style="width:391px" %)(((
622 622  Each bit can control the mask of an interrupt.
623 623  
624 -ON: Mask interrupt OFF: Enable interrupt
625 -)))|0
626 -|SD355|81st to 96th timer interrupt|(((
623 +ON: shield interrupts; OFF: interrupt allowed
624 +)))|(% style="width:110px" %)0
625 +|SD355|(% style="width:311px" %)81st to 96th timer interrupt|(% style="width:391px" %)(((
627 627  Each bit can control the mask of an interrupt.
628 628  
629 -ON: Mask interrupt OFF: Enable interrupt
630 -)))|0
631 -|SD356|97th to 100th timer interrupt|(((
628 +ON: shield interrupts; OFF: interrupt allowed
629 +)))|(% style="width:110px" %)0
630 +|SD356|(% style="width:311px" %)97th to 100th timer interrupt|(% style="width:391px" %)(((
632 632  Each bit can control the mask of an interrupt.
633 633  
634 -ON: Mask interrupt OFF: Enable interrupt
635 -)))|0
633 +ON: shield interrupts; OFF: interrupt allowed
634 +)))|(% style="width:110px" %)0
636 636  
637 637  1. high-speed counter interrupt mask register
638 638  
639 639  (% class="table-bordered" %)
640 -|(% colspan="4" %)**High-speed counter interrupt mask register**
641 -|**Special register number**|**Type of interrupt**|**Instruction**|**Default**
642 -|SD382|1st to 16th high-speed counter interrupt|(((
639 +|=(% colspan="4" %)**High-speed counter interrupt mask register**
640 +|=(% style="width: 230px;" %)**Special register number**|=(% style="width: 348px;" %)**Type of interrupt**|=(% style="width: 387px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
641 +|(% style="width:230px" %)SD382|(% style="width:348px" %)1st to 16th high-speed counter interrupt|(% style="width:387px" %)(((
643 643  Each bit can control the mask of an interrupt.
644 644  
645 -ON: Mask interrupt OFF: Enable interrupt
646 -)))|0
647 -|SD383|17th to 32nd high-speed counter interrupt|(((
644 +ON: shield interrupts; OFF: interrupt allowed
645 +)))|(% style="width:110px" %)0
646 +|(% style="width:230px" %)SD383|(% style="width:348px" %)17th to 32nd high-speed counter interrupt|(% style="width:387px" %)(((
648 648  Each bit can control the mask of an interrupt.
649 649  
650 -ON: Mask interrupt OFF: Enable interrupt
651 -)))|0
652 -|SD384|33th to 48th high-speed counter interrupt|(((
649 +ON: shield interrupts; OFF: interrupt allowed
650 +)))|(% style="width:110px" %)0
651 +|(% style="width:230px" %)SD384|(% style="width:348px" %)33th to 48th high-speed counter interrupt|(% style="width:387px" %)(((
653 653  Each bit can control the mask of an interrupt.
654 654  
655 -ON: Mask interrupt OFF: Enable interrupt
656 -)))|0
657 -|SD385|49th to 64th high-speed counter interrupt|(((
654 +ON: shield interrupts; OFF: interrupt allowed
655 +)))|(% style="width:110px" %)0
656 +|(% style="width:230px" %)SD385|(% style="width:348px" %)49th to 64th high-speed counter interrupt|(% style="width:387px" %)(((
658 658  Each bit can control the mask of an interrupt.
659 659  
660 -ON: Mask interrupt OFF: Enable interrupt
661 -)))|0
662 -|SD386|65th to 80th high-speed counter interrupt|(((
659 +ON: shield interrupts; OFF: interrupt allowed
660 +)))|(% style="width:110px" %)0
661 +|(% style="width:230px" %)SD386|(% style="width:348px" %)65th to 80th high-speed counter interrupt|(% style="width:387px" %)(((
663 663  Each bit can control the mask of an interrupt.
664 664  
665 -ON: Mask interrupt OFF: Enable interrupt
666 -)))|0
667 -|SD387|81st to 96th high-speed counter interrupt|(((
664 +ON: shield interrupts; OFF: interrupt allowed
665 +)))|(% style="width:110px" %)0
666 +|(% style="width:230px" %)SD387|(% style="width:348px" %)81st to 96th high-speed counter interrupt|(% style="width:387px" %)(((
668 668  Each bit can control the mask of an interrupt.
669 669  
670 -ON: Mask interrupt OFF: Enable interrupt
671 -)))|0
672 -|SD388|97th to 100th high-speed counter interrupt|(((
669 +ON: shield interrupts; OFF: interrupt allowed
670 +)))|(% style="width:110px" %)0
671 +|(% style="width:230px" %)SD388|(% style="width:348px" %)97th to 100th high-speed counter interrupt|(% style="width:387px" %)(((
673 673  Each bit can control the mask of an interrupt.
674 674  
675 -ON: Mask interrupt OFF: Enable interrupt
676 -)))|0
674 +ON: shield interrupts; OFF: interrupt allowed
675 +)))|(% style="width:110px" %)0
677 677  
678 678  == Subroutine ==
679 679