Changes for page 01 Program execution

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...	...	@@ -361,7 +361,6 @@
361	361	* During the execution of the interrupt program, when an interrupt cause with a low priority or the same priority occurs.
362	362	** The interruption cause that occurred is stored, and after the interrupt program in execution ends, the interrupt program corresponding to the stored interruption cause is executed. Even if the same interruption cause occurs multiple times, the interruption cause is stored only once.
363	363
364		-
365	365	(% style="text-align:center" %)
366	366	[[image:1652249673420-476.png||class="img-thumbnail"]]
367	367
...	...	@@ -577,107 +577,103 @@
577	577
578	578	(% class="table-bordered" %)
579	579	|=(% colspan="4" %)**External input interrupt mask register**
580		-|=**Special register number**|=**Type of interrupt**|=**Instruction**|=**Defaults**
581		-|SM352|X0 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
582		-|SM353|X0 falling edge interrupt|(((
583		-ON: Ma
	579	+|=(% style="width: 266px;" %)**Special register number**|=(% style="width: 308px;" %)**Type of interrupt**|=(% style="width: 390px;" %)**Instruction**|=**Defaults**
	580	+|(% style="width:266px" %)SM352|(% style="width:308px" %)X0 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	581	+|(% style="width:266px" %)SM353|(% style="width:308px" %)X0 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	582	+|(% style="width:266px" %)SM354|(% style="width:308px" %)X1 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	583	+|(% style="width:266px" %)SM355|(% style="width:308px" %)X1 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	584	+|(% style="width:266px" %)SM356|(% style="width:308px" %)X2 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	585	+|(% style="width:266px" %)SM357|(% style="width:308px" %)X2 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	586	+|(% style="width:266px" %)SM358|(% style="width:308px" %)X3 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	587	+|(% style="width:266px" %)SM359|(% style="width:308px" %)X3 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
	588	+|(% style="width:266px" %)SM360|(% style="width:308px" %)X4 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	589	+|(% style="width:266px" %)SM361|(% style="width:308px" %)X4 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	590	+|(% style="width:266px" %)SM362|(% style="width:308px" %)X5 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	591	+|(% style="width:266px" %)SM363|(% style="width:308px" %)X5 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
	592	+|(% style="width:266px" %)SM364|(% style="width:308px" %)X6 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	593	+|(% style="width:266px" %)SM365|(% style="width:308px" %)X6 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	594	+|(% style="width:266px" %)SM366|(% style="width:308px" %)X7 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	595	+|(% style="width:266px" %)SM367|(% style="width:308px" %)X7 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
584	584
585		-sk interrupt OFF: Enable interrupt
586		-)))|OFF
587		-|SM354|X1 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
588		-|SM355|X1 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
589		-|SM356|X2 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
590		-|SM357|X2 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
591		-|SM358|X3 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
592		-|SM359|X3 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
593		-|SM360|X4 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
594		-|SM361|X4 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
595		-|SM362|X5 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
596		-|SM363|X5 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
597		-|SM364|X6 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
598		-|SM365|X6 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
599		-|SM366|X7 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
600		-|SM367|X7 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
601		-
602	602	(% class="table-bordered" %)
603	603	|=(% colspan="4" %)**Timer interrupt mask register**
604		-|=**Special register number**|=**Type of interrupt**|=**Instruction**|=**Default**
605		-|SD350|1st to 16th timer interrupt|(((
	599	+|=**Special register number**|=(% style="width: 311px;" %)**Type of interrupt**|=(% style="width: 391px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
	600	+|SD350|(% style="width:311px" %)1st to 16th timer interrupt|(% style="width:391px" %)(((
606	606	Each bit can control the mask of an interrupt.
607	607
608		-ON: Mask interrupt OFF: Enable interrupt
609		-)))|0
610		-|SD351|17th to 32th timer interrupt|(((
	603	+ON: shield interrupts; OFF: interrupt allowed
	604	+)))|(% style="width:110px" %)0
	605	+|SD351|(% style="width:311px" %)17th to 32th timer interrupt|(% style="width:391px" %)(((
611	611	Each bit can control the mask of an interrupt.
612	612
613		-ON: Mask interrupt OFF: Enable interrupt
614		-)))|0
615		-|SD352|33th to 48th timer interrupt|(((
	608	+ON: shield interrupts; OFF: interrupt allowed
	609	+)))|(% style="width:110px" %)0
	610	+|SD352|(% style="width:311px" %)33th to 48th timer interrupt|(% style="width:391px" %)(((
616	616	Each bit can control the mask of an interrupt.
617	617
618		-ON: Mask interrupt OFF: Enable interrupt
619		-)))|0
620		-|SD353|49th to 64th timer interrupt|(((
	613	+ON: shield interrupts; OFF: interrupt allowed
	614	+)))|(% style="width:110px" %)0
	615	+|SD353|(% style="width:311px" %)49th to 64th timer interrupt|(% style="width:391px" %)(((
621	621	Each bit can control the mask of an interrupt.
622	622
623		-ON: Mask interrupt OFF: Enable interrupt
624		-)))|0
625		-|SD354|65th to 80th timer interrupt|(((
	618	+ON: shield interrupts; OFF: interrupt allowed
	619	+)))|(% style="width:110px" %)0
	620	+|SD354|(% style="width:311px" %)65th to 80th timer interrupt|(% style="width:391px" %)(((
626	626	Each bit can control the mask of an interrupt.
627	627
628		-ON: Mask interrupt OFF: Enable interrupt
629		-)))|0
630		-|SD355|81st to 96th timer interrupt|(((
	623	+ON: shield interrupts; OFF: interrupt allowed
	624	+)))|(% style="width:110px" %)0
	625	+|SD355|(% style="width:311px" %)81st to 96th timer interrupt|(% style="width:391px" %)(((
631	631	Each bit can control the mask of an interrupt.
632	632
633		-ON: Mask interrupt OFF: Enable interrupt
634		-)))|0
635		-|SD356|97th to 100th timer interrupt|(((
	628	+ON: shield interrupts; OFF: interrupt allowed
	629	+)))|(% style="width:110px" %)0
	630	+|SD356|(% style="width:311px" %)97th to 100th timer interrupt|(% style="width:391px" %)(((
636	636	Each bit can control the mask of an interrupt.
637	637
638		-ON: Mask interrupt OFF: Enable interrupt
639		-)))|0
	633	+ON: shield interrupts; OFF: interrupt allowed
	634	+)))|(% style="width:110px" %)0
640	640
641	641	1. high-speed counter interrupt mask register
642	642
643	643	(% class="table-bordered" %)
644		-|(% colspan="4" %)**High-speed counter interrupt mask register**
645		-|**Special register number**|**Type of interrupt**|**Instruction**|**Default**
646		-|SD382|1st to 16th high-speed counter interrupt|(((
	639	+|=(% colspan="4" %)**High-speed counter interrupt mask register**
	640	+|=(% style="width: 230px;" %)**Special register number**|=(% style="width: 348px;" %)**Type of interrupt**|=(% style="width: 387px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
	641	+|(% style="width:230px" %)SD382|(% style="width:348px" %)1st to 16th high-speed counter interrupt|(% style="width:387px" %)(((
647	647	Each bit can control the mask of an interrupt.
648	648
649		-ON: Mask interrupt OFF: Enable interrupt
650		-)))|0
651		-|SD383|17th to 32nd high-speed counter interrupt|(((
	644	+ON: shield interrupts; OFF: interrupt allowed
	645	+)))|(% style="width:110px" %)0
	646	+|(% style="width:230px" %)SD383|(% style="width:348px" %)17th to 32nd high-speed counter interrupt|(% style="width:387px" %)(((
652	652	Each bit can control the mask of an interrupt.
653	653
654		-ON: Mask interrupt OFF: Enable interrupt
655		-)))|0
656		-|SD384|33th to 48th high-speed counter interrupt|(((
	649	+ON: shield interrupts; OFF: interrupt allowed
	650	+)))|(% style="width:110px" %)0
	651	+|(% style="width:230px" %)SD384|(% style="width:348px" %)33th to 48th high-speed counter interrupt|(% style="width:387px" %)(((
657	657	Each bit can control the mask of an interrupt.
658	658
659		-ON: Mask interrupt OFF: Enable interrupt
660		-)))|0
661		-|SD385|49th to 64th high-speed counter interrupt|(((
	654	+ON: shield interrupts; OFF: interrupt allowed
	655	+)))|(% style="width:110px" %)0
	656	+|(% style="width:230px" %)SD385|(% style="width:348px" %)49th to 64th high-speed counter interrupt|(% style="width:387px" %)(((
662	662	Each bit can control the mask of an interrupt.
663	663
664		-ON: Mask interrupt OFF: Enable interrupt
665		-)))|0
666		-|SD386|65th to 80th high-speed counter interrupt|(((
	659	+ON: shield interrupts; OFF: interrupt allowed
	660	+)))|(% style="width:110px" %)0
	661	+|(% style="width:230px" %)SD386|(% style="width:348px" %)65th to 80th high-speed counter interrupt|(% style="width:387px" %)(((
667	667	Each bit can control the mask of an interrupt.
668	668
669		-ON: Mask interrupt OFF: Enable interrupt
670		-)))|0
671		-|SD387|81st to 96th high-speed counter interrupt|(((
	664	+ON: shield interrupts; OFF: interrupt allowed
	665	+)))|(% style="width:110px" %)0
	666	+|(% style="width:230px" %)SD387|(% style="width:348px" %)81st to 96th high-speed counter interrupt|(% style="width:387px" %)(((
672	672	Each bit can control the mask of an interrupt.
673	673
674		-ON: Mask interrupt OFF: Enable interrupt
675		-)))|0
676		-|SD388|97th to 100th high-speed counter interrupt|(((
	669	+ON: shield interrupts; OFF: interrupt allowed
	670	+)))|(% style="width:110px" %)0
	671	+|(% style="width:230px" %)SD388|(% style="width:348px" %)97th to 100th high-speed counter interrupt|(% style="width:387px" %)(((
677	677	Each bit can control the mask of an interrupt.
678	678
679		-ON: Mask interrupt OFF: Enable interrupt
680		-)))|0
	674	+ON: shield interrupts; OFF: interrupt allowed
	675	+)))|(% style="width:110px" %)0
681	681
682	682	== Subroutine ==
683	683