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Changes for page 01 Program execution

Last modified by Jiahao Lai on 2025/07/18 17:39
From version 16.1
edited by Stone Wu
on 2022/09/23 16:31
Change comment: There is no comment for this version
To version 15.1
edited by Stone Wu
on 2022/09/23 16:24
Change comment: There is no comment for this version

Summary

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Content
... ... @@ -576,103 +576,107 @@
576 576  
577 577  (% class="table-bordered" %)
578 578  |=(% colspan="4" %)**External input interrupt mask register**
579 -|=(% style="width: 266px;" %)**Special register number**|=(% style="width: 308px;" %)**Type of interrupt**|=(% style="width: 390px;" %)**Instruction**|=**Defaults**
580 -|(% style="width:266px" %)SM352|(% style="width:308px" %)X0 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
581 -|(% style="width:266px" %)SM353|(% style="width:308px" %)X0 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
582 -|(% style="width:266px" %)SM354|(% style="width:308px" %)X1 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
583 -|(% style="width:266px" %)SM355|(% style="width:308px" %)X1 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
584 -|(% style="width:266px" %)SM356|(% style="width:308px" %)X2 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
585 -|(% style="width:266px" %)SM357|(% style="width:308px" %)X2 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
586 -|(% style="width:266px" %)SM358|(% style="width:308px" %)X3 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
587 -|(% style="width:266px" %)SM359|(% style="width:308px" %)X3 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
588 -|(% style="width:266px" %)SM360|(% style="width:308px" %)X4 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
589 -|(% style="width:266px" %)SM361|(% style="width:308px" %)X4 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
590 -|(% style="width:266px" %)SM362|(% style="width:308px" %)X5 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
591 -|(% style="width:266px" %)SM363|(% style="width:308px" %)X5 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
592 -|(% style="width:266px" %)SM364|(% style="width:308px" %)X6 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
593 -|(% style="width:266px" %)SM365|(% style="width:308px" %)X6 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
594 -|(% style="width:266px" %)SM366|(% style="width:308px" %)X7 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
595 -|(% style="width:266px" %)SM367|(% style="width:308px" %)X7 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
579 +|=**Special register number**|=**Type of interrupt**|=**Instruction**|=**Defaults**
580 +|SM352|X0 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
581 +|SM353|X0 falling edge interrupt|(((
582 +ON: Ma
596 596  
584 +sk interrupt OFF: Enable interrupt
585 +)))|OFF
586 +|SM354|X1 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
587 +|SM355|X1 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
588 +|SM356|X2 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
589 +|SM357|X2 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
590 +|SM358|X3 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
591 +|SM359|X3 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
592 +|SM360|X4 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
593 +|SM361|X4 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
594 +|SM362|X5 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
595 +|SM363|X5 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
596 +|SM364|X6 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
597 +|SM365|X6 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
598 +|SM366|X7 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
599 +|SM367|X7 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
600 +
597 597  (% class="table-bordered" %)
598 598  |=(% colspan="4" %)**Timer interrupt mask register**
599 -|=**Special register number**|=(% style="width: 311px;" %)**Type of interrupt**|=(% style="width: 391px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
600 -|SD350|(% style="width:311px" %)1st to 16th timer interrupt|(% style="width:391px" %)(((
603 +|=**Special register number**|=**Type of interrupt**|=**Instruction**|=**Default**
604 +|SD350|1st to 16th timer interrupt|(((
601 601  Each bit can control the mask of an interrupt.
602 602  
603 -ON: shield interrupts; OFF: interrupt allowed
604 -)))|(% style="width:110px" %)0
605 -|SD351|(% style="width:311px" %)17th to 32th timer interrupt|(% style="width:391px" %)(((
607 +ON: Mask interrupt OFF: Enable interrupt
608 +)))|0
609 +|SD351|17th to 32th timer interrupt|(((
606 606  Each bit can control the mask of an interrupt.
607 607  
608 -ON: shield interrupts; OFF: interrupt allowed
609 -)))|(% style="width:110px" %)0
610 -|SD352|(% style="width:311px" %)33th to 48th timer interrupt|(% style="width:391px" %)(((
612 +ON: Mask interrupt OFF: Enable interrupt
613 +)))|0
614 +|SD352|33th to 48th timer interrupt|(((
611 611  Each bit can control the mask of an interrupt.
612 612  
613 -ON: shield interrupts; OFF: interrupt allowed
614 -)))|(% style="width:110px" %)0
615 -|SD353|(% style="width:311px" %)49th to 64th timer interrupt|(% style="width:391px" %)(((
617 +ON: Mask interrupt OFF: Enable interrupt
618 +)))|0
619 +|SD353|49th to 64th timer interrupt|(((
616 616  Each bit can control the mask of an interrupt.
617 617  
618 -ON: shield interrupts; OFF: interrupt allowed
619 -)))|(% style="width:110px" %)0
620 -|SD354|(% style="width:311px" %)65th to 80th timer interrupt|(% style="width:391px" %)(((
622 +ON: Mask interrupt OFF: Enable interrupt
623 +)))|0
624 +|SD354|65th to 80th timer interrupt|(((
621 621  Each bit can control the mask of an interrupt.
622 622  
623 -ON: shield interrupts; OFF: interrupt allowed
624 -)))|(% style="width:110px" %)0
625 -|SD355|(% style="width:311px" %)81st to 96th timer interrupt|(% style="width:391px" %)(((
627 +ON: Mask interrupt OFF: Enable interrupt
628 +)))|0
629 +|SD355|81st to 96th timer interrupt|(((
626 626  Each bit can control the mask of an interrupt.
627 627  
628 -ON: shield interrupts; OFF: interrupt allowed
629 -)))|(% style="width:110px" %)0
630 -|SD356|(% style="width:311px" %)97th to 100th timer interrupt|(% style="width:391px" %)(((
632 +ON: Mask interrupt OFF: Enable interrupt
633 +)))|0
634 +|SD356|97th to 100th timer interrupt|(((
631 631  Each bit can control the mask of an interrupt.
632 632  
633 -ON: shield interrupts; OFF: interrupt allowed
634 -)))|(% style="width:110px" %)0
637 +ON: Mask interrupt OFF: Enable interrupt
638 +)))|0
635 635  
636 636  1. high-speed counter interrupt mask register
637 637  
638 638  (% class="table-bordered" %)
639 -|=(% colspan="4" %)**High-speed counter interrupt mask register**
640 -|=(% style="width: 230px;" %)**Special register number**|=(% style="width: 348px;" %)**Type of interrupt**|=(% style="width: 387px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
641 -|(% style="width:230px" %)SD382|(% style="width:348px" %)1st to 16th high-speed counter interrupt|(% style="width:387px" %)(((
643 +|(% colspan="4" %)**High-speed counter interrupt mask register**
644 +|**Special register number**|**Type of interrupt**|**Instruction**|**Default**
645 +|SD382|1st to 16th high-speed counter interrupt|(((
642 642  Each bit can control the mask of an interrupt.
643 643  
644 -ON: shield interrupts; OFF: interrupt allowed
645 -)))|(% style="width:110px" %)0
646 -|(% style="width:230px" %)SD383|(% style="width:348px" %)17th to 32nd high-speed counter interrupt|(% style="width:387px" %)(((
648 +ON: Mask interrupt OFF: Enable interrupt
649 +)))|0
650 +|SD383|17th to 32nd high-speed counter interrupt|(((
647 647  Each bit can control the mask of an interrupt.
648 648  
649 -ON: shield interrupts; OFF: interrupt allowed
650 -)))|(% style="width:110px" %)0
651 -|(% style="width:230px" %)SD384|(% style="width:348px" %)33th to 48th high-speed counter interrupt|(% style="width:387px" %)(((
653 +ON: Mask interrupt OFF: Enable interrupt
654 +)))|0
655 +|SD384|33th to 48th high-speed counter interrupt|(((
652 652  Each bit can control the mask of an interrupt.
653 653  
654 -ON: shield interrupts; OFF: interrupt allowed
655 -)))|(% style="width:110px" %)0
656 -|(% style="width:230px" %)SD385|(% style="width:348px" %)49th to 64th high-speed counter interrupt|(% style="width:387px" %)(((
658 +ON: Mask interrupt OFF: Enable interrupt
659 +)))|0
660 +|SD385|49th to 64th high-speed counter interrupt|(((
657 657  Each bit can control the mask of an interrupt.
658 658  
659 -ON: shield interrupts; OFF: interrupt allowed
660 -)))|(% style="width:110px" %)0
661 -|(% style="width:230px" %)SD386|(% style="width:348px" %)65th to 80th high-speed counter interrupt|(% style="width:387px" %)(((
663 +ON: Mask interrupt OFF: Enable interrupt
664 +)))|0
665 +|SD386|65th to 80th high-speed counter interrupt|(((
662 662  Each bit can control the mask of an interrupt.
663 663  
664 -ON: shield interrupts; OFF: interrupt allowed
665 -)))|(% style="width:110px" %)0
666 -|(% style="width:230px" %)SD387|(% style="width:348px" %)81st to 96th high-speed counter interrupt|(% style="width:387px" %)(((
668 +ON: Mask interrupt OFF: Enable interrupt
669 +)))|0
670 +|SD387|81st to 96th high-speed counter interrupt|(((
667 667  Each bit can control the mask of an interrupt.
668 668  
669 -ON: shield interrupts; OFF: interrupt allowed
670 -)))|(% style="width:110px" %)0
671 -|(% style="width:230px" %)SD388|(% style="width:348px" %)97th to 100th high-speed counter interrupt|(% style="width:387px" %)(((
673 +ON: Mask interrupt OFF: Enable interrupt
674 +)))|0
675 +|SD388|97th to 100th high-speed counter interrupt|(((
672 672  Each bit can control the mask of an interrupt.
673 673  
674 -ON: shield interrupts; OFF: interrupt allowed
675 -)))|(% style="width:110px" %)0
678 +ON: Mask interrupt OFF: Enable interrupt
679 +)))|0
676 676  
677 677  == Subroutine ==
678 678