Changes for page 01 Program execution

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...	...	@@ -361,6 +361,7 @@
361	361	* During the execution of the interrupt program, when an interrupt cause with a low priority or the same priority occurs.
362	362	** The interruption cause that occurred is stored, and after the interrupt program in execution ends, the interrupt program corresponding to the stored interruption cause is executed. Even if the same interruption cause occurs multiple times, the interruption cause is stored only once.
363	363
	364	+
364	364	(% style="text-align:center" %)
365	365	[[image:1652249673420-476.png||class="img-thumbnail"]]
366	366
...	...	@@ -576,107 +576,107 @@
576	576
577	577	(% class="table-bordered" %)
578	578	|=(% colspan="4" %)**External input interrupt mask register**
579		-|=(% style="width: 266px;" %)**Special register number**|=(% style="width: 308px;" %)**Type of interrupt**|=(% style="width: 390px;" %)**Instruction**|=**Defaults**
580		-|(% style="width:266px" %)SM352|(% style="width:308px" %)X0 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
581		-|(% style="width:266px" %)SM353|(% style="width:308px" %)X0 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
582		-|(% style="width:266px" %)SM354|(% style="width:308px" %)X1 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
583		-|(% style="width:266px" %)SM355|(% style="width:308px" %)X1 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
584		-|(% style="width:266px" %)SM356|(% style="width:308px" %)X2 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
585		-|(% style="width:266px" %)SM357|(% style="width:308px" %)X2 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
586		-|(% style="width:266px" %)SM358|(% style="width:308px" %)X3 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
587		-|(% style="width:266px" %)SM359|(% style="width:308px" %)X3 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
588		-|(% style="width:266px" %)SM360|(% style="width:308px" %)X4 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
589		-|(% style="width:266px" %)SM361|(% style="width:308px" %)X4 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
590		-|(% style="width:266px" %)SM362|(% style="width:308px" %)X5 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
591		-|(% style="width:266px" %)SM363|(% style="width:308px" %)X5 falling edge interrupt|(% style="width:390px" %)ON: Shield interrupts; OFF: interrupt allowed|OFF
592		-|(% style="width:266px" %)SM364|(% style="width:308px" %)X6 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
593		-|(% style="width:266px" %)SM365|(% style="width:308px" %)X6 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
594		-|(% style="width:266px" %)SM366|(% style="width:308px" %)X7 rising edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
595		-|(% style="width:266px" %)SM367|(% style="width:308px" %)X7 falling edge interrupt|(% style="width:390px" %)ON: shield interrupts; OFF: interrupt allowed|OFF
	580	+|=**Special register number**|=**Type of interrupt**|=**Instruction**|=**Defaults**
	581	+|SM352|X0 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	582	+|SM353|X0 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	583	+|SM354|X1 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	584	+|SM355|X1 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	585	+|SM356|X2 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	586	+|SM357|X2 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	587	+|SM358|X3 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	588	+|SM359|X3 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	589	+|SM360|X4 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	590	+|SM361|X4 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	591	+|SM362|X5 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	592	+|SM363|X5 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	593	+|SM364|X6 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	594	+|SM365|X6 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	595	+|SM366|X7 rising edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
	596	+|SM367|X7 falling edge interrupt|ON: Mask interrupt OFF: Enable interrupt|OFF
596	596
597	597	(% class="table-bordered" %)
598		-|=(% colspan="4" %)**Timer interrupt mask register**
599		-|=**Special register number**|=(% style="width: 311px;" %)**Type of interrupt**|=(% style="width: 391px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
600		-|SD350|(% style="width:311px" %)1st to 16th timer interrupt|(% style="width:391px" %)(((
	599	+|(% colspan="4" %)**Timer interrupt mask register**
	600	+|**Special register number**|**Type of interrupt**|**Instruction**|**Default**
	601	+|SD350|1st to 16th timer interrupt|(((
601	601	Each bit can control the mask of an interrupt.
602	602
603		-ON: shield interrupts; OFF: interrupt allowed
604		-)))|(% style="width:110px" %)0
605		-|SD351|(% style="width:311px" %)17th to 32th timer interrupt|(% style="width:391px" %)(((
	604	+ON: Mask interrupt OFF: Enable interrupt
	605	+)))|0
	606	+|SD351|17th to 32th timer interrupt|(((
606	606	Each bit can control the mask of an interrupt.
607	607
608		-ON: shield interrupts; OFF: interrupt allowed
609		-)))|(% style="width:110px" %)0
610		-|SD352|(% style="width:311px" %)33th to 48th timer interrupt|(% style="width:391px" %)(((
	609	+ON: Mask interrupt OFF: Enable interrupt
	610	+)))|0
	611	+|SD352|33th to 48th timer interrupt|(((
611	611	Each bit can control the mask of an interrupt.
612	612
613		-ON: shield interrupts; OFF: interrupt allowed
614		-)))|(% style="width:110px" %)0
615		-|SD353|(% style="width:311px" %)49th to 64th timer interrupt|(% style="width:391px" %)(((
	614	+ON: Mask interrupt OFF: Enable interrupt
	615	+)))|0
	616	+|SD353|49th to 64th timer interrupt|(((
616	616	Each bit can control the mask of an interrupt.
617	617
618		-ON: shield interrupts; OFF: interrupt allowed
619		-)))|(% style="width:110px" %)0
620		-|SD354|(% style="width:311px" %)65th to 80th timer interrupt|(% style="width:391px" %)(((
	619	+ON: Mask interrupt OFF: Enable interrupt
	620	+)))|0
	621	+|SD354|65th to 80th timer interrupt|(((
621	621	Each bit can control the mask of an interrupt.
622	622
623		-ON: shield interrupts; OFF: interrupt allowed
624		-)))|(% style="width:110px" %)0
625		-|SD355|(% style="width:311px" %)81st to 96th timer interrupt|(% style="width:391px" %)(((
	624	+ON: Mask interrupt OFF: Enable interrupt
	625	+)))|0
	626	+|SD355|81st to 96th timer interrupt|(((
626	626	Each bit can control the mask of an interrupt.
627	627
628		-ON: shield interrupts; OFF: interrupt allowed
629		-)))|(% style="width:110px" %)0
630		-|SD356|(% style="width:311px" %)97th to 100th timer interrupt|(% style="width:391px" %)(((
	629	+ON: Mask interrupt OFF: Enable interrupt
	630	+)))|0
	631	+|SD356|97th to 100th timer interrupt|(((
631	631	Each bit can control the mask of an interrupt.
632	632
633		-ON: shield interrupts; OFF: interrupt allowed
634		-)))|(% style="width:110px" %)0
	634	+ON: Mask interrupt OFF: Enable interrupt
	635	+)))|0
635	635
636	636	1. high-speed counter interrupt mask register
637	637
638	638	(% class="table-bordered" %)
639		-|=(% colspan="4" %)**High-speed counter interrupt mask register**
640		-|=(% style="width: 230px;" %)**Special register number**|=(% style="width: 348px;" %)**Type of interrupt**|=(% style="width: 387px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
641		-|(% style="width:230px" %)SD382|(% style="width:348px" %)1st to 16th high-speed counter interrupt|(% style="width:387px" %)(((
	640	+|(% colspan="4" %)**High-speed counter interrupt mask register**
	641	+|**Special register number**|**Type of interrupt**|**Instruction**|**Default**
	642	+|SD382|1st to 16th high-speed counter interrupt|(((
642	642	Each bit can control the mask of an interrupt.
643	643
644		-ON: shield interrupts; OFF: interrupt allowed
645		-)))|(% style="width:110px" %)0
646		-|(% style="width:230px" %)SD383|(% style="width:348px" %)17th to 32nd high-speed counter interrupt|(% style="width:387px" %)(((
	645	+ON: Mask interrupt OFF: Enable interrupt
	646	+)))|0
	647	+|SD383|17th to 32nd high-speed counter interrupt|(((
647	647	Each bit can control the mask of an interrupt.
648	648
649		-ON: shield interrupts; OFF: interrupt allowed
650		-)))|(% style="width:110px" %)0
651		-|(% style="width:230px" %)SD384|(% style="width:348px" %)33th to 48th high-speed counter interrupt|(% style="width:387px" %)(((
	650	+ON: Mask interrupt OFF: Enable interrupt
	651	+)))|0
	652	+|SD384|33th to 48th high-speed counter interrupt|(((
652	652	Each bit can control the mask of an interrupt.
653	653
654		-ON: shield interrupts; OFF: interrupt allowed
655		-)))|(% style="width:110px" %)0
656		-|(% style="width:230px" %)SD385|(% style="width:348px" %)49th to 64th high-speed counter interrupt|(% style="width:387px" %)(((
	655	+ON: Mask interrupt OFF: Enable interrupt
	656	+)))|0
	657	+|SD385|49th to 64th high-speed counter interrupt|(((
657	657	Each bit can control the mask of an interrupt.
658	658
659		-ON: shield interrupts; OFF: interrupt allowed
660		-)))|(% style="width:110px" %)0
661		-|(% style="width:230px" %)SD386|(% style="width:348px" %)65th to 80th high-speed counter interrupt|(% style="width:387px" %)(((
	660	+ON: Mask interrupt OFF: Enable interrupt
	661	+)))|0
	662	+|SD386|65th to 80th high-speed counter interrupt|(((
662	662	Each bit can control the mask of an interrupt.
663	663
664		-ON: shield interrupts; OFF: interrupt allowed
665		-)))|(% style="width:110px" %)0
666		-|(% style="width:230px" %)SD387|(% style="width:348px" %)81st to 96th high-speed counter interrupt|(% style="width:387px" %)(((
	665	+ON: Mask interrupt OFF: Enable interrupt
	666	+)))|0
	667	+|SD387|81st to 96th high-speed counter interrupt|(((
667	667	Each bit can control the mask of an interrupt.
668	668
669		-ON: shield interrupts; OFF: interrupt allowed
670		-)))|(% style="width:110px" %)0
671		-|(% style="width:230px" %)SD388|(% style="width:348px" %)97th to 100th high-speed counter interrupt|(% style="width:387px" %)(((
	670	+ON: Mask interrupt OFF: Enable interrupt
	671	+)))|0
	672	+|SD388|97th to 100th high-speed counter interrupt|(((
672	672	Each bit can control the mask of an interrupt.
673	673
674		-ON: shield interrupts; OFF: interrupt allowed
675		-)))|(% style="width:110px" %)0
	675	+ON: Mask interrupt OFF: Enable interrupt
	676	+)))|0
676	676
677	677	== Subroutine ==
678	678
679		-During the execution of the scan program, the executed program can be called by the CALL instruction. You can create up to 100 new subprograms.
	680	+During the execution of the scan program, the executed program can be called by the CALL instruction.
680	680
681	681	A subroutine is to split a certain module in the main program for the main program to call, which is conducive to the modularization of the program. Such as other high-level language functions, but this function has no parameters and no return value.
682	682
...	...	@@ -683,7 +683,7 @@
683	683	(% style="text-align:center" %)
684	684	[[image:1652250926997-587.png||class="img-thumbnail"]]
685	685
686		-**Instructions for calling subroutines**
	687	+1. Instructions for calling subroutines
687	687
688	688	After a new subroutine is created, the content of the program is not executed. It is executed only when the CALL(P) instruction is used to call the subroutine in the scan, event, and interrupt programs, and the call is executed once. Three new subroutines SUB0, SUB1, SUB2 are created as shown in the figure below. In the main program MAIN, the subprogram can be called by using the CALL(P) subprogram program name.
689	689
...	...	@@ -692,15 +692,12 @@
692	692	(% style="text-align:center" %)
693	693	[[image:1-28.png||class="img-thumbnail"]]
694	694
695		-(% class="box infomessage" %)
696		-(((
697		-**✎Note:**
	696	+**~ 1.✎Note:**
698	698
699	699	1. When using the timer (OUT T), note that the output will not be reset when the subroutine is not called, and a specific subroutine register must be used.
700	700	1. It is not allowed to call recursively between subprograms, that is, call SUB1 in SUB0, and then call SUB0 in SUB1. This is not allowed.
701	701	1. The subroutine can be nested up to 32 levels. If the level exceeds 32 levels, a serious error will be reported and the Circuit program operation will be forcibly stopped.
702	702	1. Unlike the LX3V series mainframe, the subroutine in the LX5V series mainframe ends with the END instruction instead of SRET.
703		-)))
704	704
705	705	== Positioning instructions ==
706	706