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Changes for page 01 Program execution

Last modified by Leo Wei on 2024/12/24 22:42
From version 25.1
edited by Jim
on 2023/07/26 15:16
Change comment: There is no comment for this version
To version 18.1
edited by Stone Wu
on 2022/09/23 16:36
Change comment: There is no comment for this version

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1 -XWiki.Jim
1 +XWiki.Stone
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131 131  The initialization based on the status of the CPU module is as follows.
132 132  
133 133  * **√**: execute
134 -* **×**: not execute
134 +* **×**: not execute
135 135  
136 136  (% class="table-bordered" %)
137 137  |=(% rowspan="2" %)**Processing item**|=(% colspan="3" %)**Status of the CPU module**
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247 247  *1: Scan program paging: multiple scan programs are established, and each scan program is called a paging. After scan program A is executed, before scan program B is executed, it will be judged whether an event program needs to be executed.
248 248  
249 249  (% style="text-align:center" %)
250 -[[image:image-20220926104203-1.jpeg||class="img-thumbnail"]]
250 +[[image:1652247397997-492.png||class="img-thumbnail"]]
251 251  
252 252  When it is the turn of the execution sequence of event execution type program C and Y50 is ON, the program is executed.
253 253  
... ... @@ -596,38 +596,38 @@
596 596  
597 597  (% class="table-bordered" %)
598 598  |=(% colspan="4" %)**Timer interrupt mask register**
599 -|=(% style="width: 262px;" %)**Special register number**|=(% style="width: 309px;" %)**Type of interrupt**|=(% style="width: 394px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
600 -|(% style="width:262px" %)SD350|(% style="width:309px" %)1st to 16th timer interrupt|(% style="width:394px" %)(((
599 +|=**Special register number**|=(% style="width: 311px;" %)**Type of interrupt**|=(% style="width: 391px;" %)**Instruction**|=(% style="width: 110px;" %)**Default**
600 +|SD350|(% style="width:311px" %)1st to 16th timer interrupt|(% style="width:391px" %)(((
601 601  Each bit can control the mask of an interrupt.
602 602  
603 603  ON: shield interrupts; OFF: interrupt allowed
604 604  )))|(% style="width:110px" %)0
605 -|(% style="width:262px" %)SD351|(% style="width:309px" %)17th to 32th timer interrupt|(% style="width:394px" %)(((
605 +|SD351|(% style="width:311px" %)17th to 32th timer interrupt|(% style="width:391px" %)(((
606 606  Each bit can control the mask of an interrupt.
607 607  
608 608  ON: shield interrupts; OFF: interrupt allowed
609 609  )))|(% style="width:110px" %)0
610 -|(% style="width:262px" %)SD352|(% style="width:309px" %)33th to 48th timer interrupt|(% style="width:394px" %)(((
610 +|SD352|(% style="width:311px" %)33th to 48th timer interrupt|(% style="width:391px" %)(((
611 611  Each bit can control the mask of an interrupt.
612 612  
613 613  ON: shield interrupts; OFF: interrupt allowed
614 614  )))|(% style="width:110px" %)0
615 -|(% style="width:262px" %)SD353|(% style="width:309px" %)49th to 64th timer interrupt|(% style="width:394px" %)(((
615 +|SD353|(% style="width:311px" %)49th to 64th timer interrupt|(% style="width:391px" %)(((
616 616  Each bit can control the mask of an interrupt.
617 617  
618 618  ON: shield interrupts; OFF: interrupt allowed
619 619  )))|(% style="width:110px" %)0
620 -|(% style="width:262px" %)SD354|(% style="width:309px" %)65th to 80th timer interrupt|(% style="width:394px" %)(((
620 +|SD354|(% style="width:311px" %)65th to 80th timer interrupt|(% style="width:391px" %)(((
621 621  Each bit can control the mask of an interrupt.
622 622  
623 623  ON: shield interrupts; OFF: interrupt allowed
624 624  )))|(% style="width:110px" %)0
625 -|(% style="width:262px" %)SD355|(% style="width:309px" %)81st to 96th timer interrupt|(% style="width:394px" %)(((
625 +|SD355|(% style="width:311px" %)81st to 96th timer interrupt|(% style="width:391px" %)(((
626 626  Each bit can control the mask of an interrupt.
627 627  
628 628  ON: shield interrupts; OFF: interrupt allowed
629 629  )))|(% style="width:110px" %)0
630 -|(% style="width:262px" %)SD356|(% style="width:309px" %)97th to 100th timer interrupt|(% style="width:394px" %)(((
630 +|SD356|(% style="width:311px" %)97th to 100th timer interrupt|(% style="width:391px" %)(((
631 631  Each bit can control the mask of an interrupt.
632 632  
633 633  ON: shield interrupts; OFF: interrupt allowed
image-20220926104203-1.jpeg
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