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Wiki source code of LS

Version 4.1 by Leo Wei on 2023/08/24 14:11
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Leo Wei 2.1 1 = {{id name="HLS"/}}LS =
2
3 == {{id name="HXBCserial"/}}**XBC serial** ==
4
5 **1）V-BOX Settings**
6
7 |**Item**|**Settings**|**Note**
8 |Protocol|LS XBC CNet|
9 |Connection|RS232|
10 |Baud rate|115200|
11 |Data bit|8|
12 |Parity|NONE|
13 |Stop bit|1|
14 |PLC station No.|1|
15
16 **2）Address List**
17
18 |**Type**|**Device registers**|**HMI registers**|**Format**|**Range**|**Note**
19 |Bit|P|P|P d|0~~2047|
20 |Bit|M|M|M d|0~~2047|
21 |Bit|L|L|L d|0~~11263|
22 |Bit|K|K|K d|0~~16183|
23 |Bit|F|F|F d|0~~2047|
24 |Bit|D|D|D d|0~~32767|
25 |Bit|R|R|R d|0~~32767|
26 |Bit|U|U|U d|0~~4095|
27 |Word|P|P|P d|0~~2047|
28 |Word|M|M|M d|0~~2047|
29 |Word|L|L|L d|0~~11263|
30 |Word|K|K|K d|0~~16183|
31 |Word|F|F|F d|0~~2047|
32 |Word|C|C|C d|0~~2047|
33 |Word|T|T|T d|0~~2047|
34 |Word|D|D|D d|0~~32767|
35 |Word|N|N|N d|0~~21503|
36 |Word|R|R|R d|0~~32767|
37 |Word|U|U|U d|0~~4095|
38 |Word|Z|Z|Z d|0~~127|
39 |Word|S|S|S d|0~~127|
40
41 **3）Configure the communication protocol**
42
43 {{id name="Iimage-20220831170147-1.png"/}}[[image:xwiki_V-BOX_V-Net_Training_1+Communication_WebHome_c40f4854ecd178d9.png||alt="image-20220831170147-1.png" height="702" width="1674"]]
44
45 **4）Cable Wiring**
46
47 Figure
48
49 {{id name="Iimage-20220831170306-4.png"/}}{{id name="Iimage-20220831170254-3.png"/}}[[image:xwiki_V-BOX_V-Net_Training_1+Communication_WebHome_b0458a3eede1f20.png||alt="image-20220831170306-4.png" height="253" width="106"]] [[image:xwiki_V-BOX_V-Net_Training_1+Communication_WebHome_bf609039f5561065.png||alt="image-20220831170254-3.png" height="170" width="480"]]
50
51 Pin Definition Diagram
52
53 {{id name="Iimage-20220831170215-2.png"/}}[[image:xwiki_V-BOX_V-Net_Training_1+Communication_WebHome_7b60fa9ec6df34a8.png||alt="image-20220831170215-2.png" height="175" width="358"]]
54
55 == {{id name="HXGKFEnetEthernet"/}}**XGK FEnet Ethernet** ==
56
57 Supported Series: LS XGT series XGK CPU with XGL-EFMT Ethernet module
58
59 **1）V-BOX Settings**
60
61 |**Items**|**Settings**|**Note**
62 |Protocol|LG XGK FEnet(Ethernet)|
63 |Connection|Ethernet|
64 |Port No.|2004|
65
66 **2）Address List**
67
68 |**Type**|**Register**|**Range**|**Format**|**Note**
69 |(% rowspan="14" %)Word|P|0~~2047|P d|
70 |M|0~~2047|M d|
71 |K|0~~2047|K d|
72 |F|0~~2047|F d|
73 |T|0~~2047|T d|
74 |C|0~~2047|C d|
75 |Z|0~~127|Z d|
76 |S|0~~127|S d|
77 |L|0~~11263|L d|
78 |N|0~~21503|N d|
79 |D|0~~32767|D d|
80 |R|0~~32767|R d|
81 |ZR|0~~65535|ZR d|
82 |UxDD|0~~6331|UxDD nndd|nn: 0~~63, dd: 0~~31
83
84 **✎Note:**
85
86 * In addition to the "UxDD" register, the others correspond to the PLC register one by one. UxDD corresponds to U in the PLC;
87 * The [UxDD] register, defined in the PLC is Ux.dd, x represents the block, and dd represents 0-31 of each block. There are 64 blocks in the PLC;
88 * All bit registers are in the form of bits in word, and the range is the same as the word register;
89
90 **3）Communication Settings**
91
92 {{id name="Iimage-20220831171127-1.png"/}}[[image:xwiki_V-BOX_V-Net_Training_1+Communication_WebHome_1775875b14c2e8e9.png||alt="image-20220831171127-1.png" height="720" width="1671"]]
93
94 **4）Cable Wiring**
95
96 {{id name="Ihttps:2F2Fdocs.we-con.com.cn2Fbin2Fdownload2FPIStudio2F12.PLC2520protocols2FWebHome2F12.PLC2520Protocol_html_2297240b57346b2a.png3Fwidth3D40126height3D17026rev3D1.1-3"/}}[[image:https://docs.we-con.com.cn/bin/download/PIStudio/12.PLC%20protocols/WebHome/12.PLC%20Protocol_html_2297240b57346b2a.png?width=401&height=170&rev=1.1||alt="12.可编程逻辑控制器Protocol_html_2297240b57346b2a.png" height="170" width="401"]]