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Wiki source code of FATEK

Version 1.2 by Hunter on 2023/09/19 14:12
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1 = FATEK ASCII =
2
3 Supported Series: FATEK FBS Series, B1 Series, B1Z Series.
4
5 **HMI Settings**
6
7 |=**Item**|=**Settings**|=**Note**
8 |Protocol|FATEK ASCII|
9 |Connection|RS232|
10 |Baud rate|9600|
11 |Data bit|7|
12 |Parity|Even|
13 |Stop bit|1|
14 |PLC station No.|0|
15
16
17 **Address List**
18
19 (% style="width:1124.22px" %)
20 |=**Type**|=**Device registers**|=(% style="width: 214px;" %)**Format**|=(% style="width: 166px;" %)**Range**|=(% style="width: 266px;" %)**Note**
21 |(% colspan="1" rowspan="7" %)Bit|X|(% style="width:214px" %)XDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Input Contact
22 |Y|(% style="width:214px" %)YDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Output Relay
23 |M|(% style="width:214px" %)MDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Internal Relay
24 |S|(% style="width:214px" %)SDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Step Relay
25 |T|(% style="width:214px" %)TDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Timer "Time-Up" Status Contact
26 |C|(% style="width:214px" %)CDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Counter "Count-Up" Status Contact
27 |(% colspan="1" %)Z|(% style="width:214px" %)ZD|(% style="width:166px" %)0|(% style="width:266px" %)
28 |(% colspan="1" rowspan="10" %)Word|(% colspan="1" %)D|(% colspan="1" style="width:214px" %)DDDDDDD|(% style="width:166px" %)0~~999999|(% style="width:266px" %)Data Register
29 |(% colspan="1" %)R|(% colspan="1" style="width:214px" %)RDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% style="width:266px" %)
30 |(% colspan="1" %)WX|(% colspan="1" style="width:214px" %)WXDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)Input Register(IR)
31 |(% colspan="1" %)WY|(% colspan="1" style="width:214px" %)WYDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)Output Register(OR)
32 |(% colspan="1" %)WM|(% colspan="1" style="width:214px" %)WMDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)
33 |(% colspan="1" %)WS|(% colspan="1" style="width:214px" %)WSDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)
34 |(% colspan="1" %)RT|(% colspan="1" style="width:214px" %)RTDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)Timer Register
35 |(% colspan="1" %)RC|(% colspan="1" style="width:214px" %)RCDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)Counter Register
36 |(% colspan="1" %)DRT|(% colspan="1" style="width:214px" %)DRTDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)Double Word Timer Register
37 |(% colspan="1" %)DRC|(% colspan="1" style="width:214px" %)DRCDDDDDD|(% colspan="1" style="width:166px" %)0~~999999|(% colspan="1" style="width:266px" %)Double Word Counter Register