09 Rotation and shift

The bit pattern of D is rotated n bits to the left on every execution. This instruction is generally used in pulse execution instruction. When the instruction is 32-bit, it occupies the subsequent neighboring address. When the device in D is KnY, KnM or KnS, only K4 (16-bit) and K8 (32-bit) is effective. The status of the last bit rotated is copied to carry flag M8022.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|D| | | | | | | |√|√|√|√|√|√|√|√|√

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|n|(% colspan="16" %)Constant, n=1~~16(16bit);n=1~~32(32-bit)

**Program example**

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[[image:7-8 Rotation and shift_html_f69c69a9d47310d7.jpg||class="img-thumbnail" height="287" width="700"]]

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= **6.9.2 ROR instruction** =

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**Instruction description**

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|ROR|(% rowspan="4" %)Make 16-bit or 32-bit data shift right|16|No|(% rowspan="4" %)ROR D n|5

|RORP|16|Yes|5

|DROR|32|No|7

|DRORP|32|Yes|7

The bit pattern of D is rotated n bits to the right on every execution. This instruction is generally used in pulse execution instruction. When the instruction is 32-bit, it occupies the subsequent neighboring address.

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When the device in D is KnY, KnM or KnS, only K4 (16-bit) and K8 (32-bit) is effective. The status of the last bit rotated is copied to carry flag M8022.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|D| | | | | | | |√|√|√|√|√|√|√|√|√

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|n|(% colspan="16" %)Constant, n=1~~16(16bit);n=1~~32(32-bit)

**Program example**

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[[image:7-8 Rotation and shift_html_97c063aafa8965c3.jpg||class="img-thumbnail" height="287" width="700"]]

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= **6.9.3 RCL instruction** =

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**Instruction description**

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|RCL|(% rowspan="4" %)Make 16-bit or 32-bit data shift left with carry|16|No|(% rowspan="4" %)RCL D n|5

|RCLP|16|Yes|5

|DRCL|32|No|9

|DRCLP|32|Yes|9

The contents of the D are rotated left n bit with the carry flag M8022. This instruction is generally used as pulse execution instruction, i.e. use the RCLP or DRCLP. When the instruction is 32bit, it takes 2 sequential addresses.

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When D is KnY or KnM or KnS, only K4 (16-bit) and K8 (32-bit) are effective.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|D| | | | | | | |√|√|√|√|√|√|√|√|√

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|n|(% colspan="16" %)Constant, n=1~~16(16bit);n=1~~32(32-bit)

**Program example**

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[[image:7-8 Rotation and shift_html_23605217c5370874.jpg||class="img-thumbnail" height="282" width="700"]]

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= **6.9.4 RCR instruction** =

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**Instruction description**

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|RCR|(% rowspan="4" %)Make 16-bit or 32-bit data shift right with carry|16|No|(% rowspan="4" %)RCR D n|5

|RCRP|16|Yes|5

|DRCR|32|No|9

|DRCRP|32|Yes|9

The contents of the D are rotated right n bit with the carry flag M8022. This instruction is generally used as pulse execution instruction, i.e. use the RCLP or DRCRP. When the instruction is 32bit, it takes 2 sequential addresses.

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When D is KnY or KnM or KnS, only K4 (16-bit) and K8 (32-bit) are effective.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|D| | | | | | | |√|√|√|√|√|√|√|√|√

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|n|(% colspan="16" %)Constant, n=1~~16(16bit);n=1~~32(32-bit)

**Program example**

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[[image:7-8 Rotation and shift_html_621a62e748d5a543.jpg||class="img-thumbnail" height="287" width="700"]]

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= **6.9.5 SFTL instruction** =

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**Instruction description**

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|SFTL|(% rowspan="2" %)Bit left shift|16|No|(% rowspan="2" %)SFTL S D n1 n2|7

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|SFTLP|16|Yes|7

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The instruction copies n2 source devices beginning form S to a bit stack of length n1 beginning from D. For every new addition of n2 bits，the existing data within the bit stack is shifted n1 bits to the left. Any bit data moving to a position exceeding the n1 limit is diverted to an overflow area.

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This instruction is generally used as pulse instruction, i.e. SFTLP.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S| |√|√|√| | | | | | | | | | | |

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|D|√|√|√|√| | | | | | | | | | | |

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|n1|(% colspan="16" %)Constant, n1≤ 1024

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|n2|(% colspan="16" %)Constant, n2≤ n1

**Program example**

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[[image:7-8 Rotation and shift_html_fdfb19f8e969cf9f.jpg||class="img-thumbnail" height="226" width="700"]]

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= **6.9.6 SFTR instruction** =

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**Instruction description**

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|SFTR|(% rowspan="2" %)Bit right shift|16|No|(% rowspan="2" %)SFTR S D n1 n2|9

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|SFTRP|16|Yes|9

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The instruction copies n2 source devices beginning form S to a bit stack of length n1 beginning from D. For every new addition of n2 bits, the existing data within the bit stack is shifted n1 bits to the right. Any bit data moving to a position exceeding the n1 limit is diverted to an overflow area.

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This instruction is generally used as pulse instruction, i.e. SFTRP.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S| |√|√|√| | | | | | | | | | | |

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|D|√|√|√|√| | | | | | | | | | | |

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|n1|(% colspan="16" %)Constant, n1≤ 1024

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|n2|(% colspan="16" %)Constant, n2≤ n1

**Program example**

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[[image:7-8 Rotation and shift_html_2db8862fde4312df.jpg||class="img-thumbnail" height="170" width="600"]]

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= **6.9.7 WSFL instruction** =

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**Instruction description**

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|WSFL|(% rowspan="2" %)Word left shift|16|No|(% rowspan="2" %)WSFL S D n1 n2|9

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|WSFLP|16|Yes|9

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The instruction copies n2 source devices to a word stack of length n1. For each addition of n2 words, the existing data within the word stack is shifted n2 words to the left. Any word data moving to a position exceeding the n1 limit is diverted to an overflow area.

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The word shifting operation will occur every time the instruction is processed unless it is modified with either the pulse suffix or a controlled interlock.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S| | | | | | | |√|√|√|√|√|√|√| |

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|D| | | | | | | | |√|√|√|√|√|√| |

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|n1|(% colspan="16" %)Constant, n1 ≤ 2048

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|n2|(% colspan="16" %)Constant, n2 ≤ n1

**Program example**

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[[image:7-8 Rotation and shift_html_bb0b90317653b219.jpg||class="img-thumbnail" height="232" width="700"]]

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= **6.9.8 WSFR instruction** =

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**Instruction description**

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|WSFR|(% rowspan="2" %)Word right shift|16|No|(% rowspan="2" %)WSFR S D n1 n2|9

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|WSFRP|16|Yes|9

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The instruction copies n2 source devices to a word stack of length n1. For each addition of n2 words, the existing data within the word stack is shifted n2 words to the right. Any word data moving to a position exceeding the n1 limit is diverted to an overflow area.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S| | | | | | | |√|√|√|√|√|√|√| |

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|D| | | | | | | | |√|√|√|√|√|√| |

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|n1|(% colspan="16" %)Constant, n1 ≤ 2048

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|n2|(% colspan="16" %)Constant, n2 ≤ n1

**Program example**

Example 1

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[[image:7-8 Rotation and shift_html_4113ad4f36c97f4c.jpg||class="img-thumbnail" height="197" width="700"]]

Example 2

When using a Kn type device, users need to specify the same number of bits.

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[[image:7-8 Rotation and shift_html_5d0aeec735d5390b.jpg||class="img-thumbnail" height="204" width="700"]]

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= **6.9.9 SFRD instruction** =

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**Instruction description**

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|SFRD|(% rowspan="2" %)Shift read (the reading instruction for controlling FIFO data)|16|No|(% rowspan="2" %)SFRD S D n|7

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|SFRDP|16|Yes|7

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The source device(S) identifies the head address of the FIFO stack. This instruction reads the first piece of data from the FIFO stack (register S+1), moves all of the data within the stack 'up' one position to fill the read area and decrements the contents of FIFO head address(S) by 1. The read data is written to the destination device (D). When the contents of source device (S) are equal to '0'(zero), i.e. the FIFO stack is empty, the flag M8020 is turned ON.

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This instruction is generally used as pulse instruction, i.e. SFRDP.

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S| | | | |√|√| |√|√|√|√|√|√|√| |

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|D| | | | | | | | |√|√|√|√|√|√| |

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|n|(% colspan="16" %)Constant, n=1~~256(16bit);n=1~~128(32-bit)

**Program example**

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[[image:7-8 Rotation and shift_html_9be7f0c2e71451ff.jpg||class="img-thumbnail" height="156" width="600"]]

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While X0 is turned from OFF to ON, this instruction executes operations according to the following orders (D10 content remains unchanged).

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1. The content in D2 is transferred to D20;

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1. D10~~D3 move a bit to right;

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1. The Indicator (D1) minus 1;

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= **6.9.10 SFWR instruction** =

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**Instruction description**

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(% class="table-bordered" %)

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|SFWR|(% rowspan="2" %)Shift write (the writing instruction for controlling FIFO data)|16|No|(% rowspan="2" %)SFWR S D n|7

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|SFWRP|16|Yes|7

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The contents of source device (S) are written to the FIFO stack. The position of insertion into stack is automatically calculated by the PLC. The destination device (D) is the head address of the FIFO stack. The contents of D identify where the next record will be stored (as an offset from D+1).

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This instruction is generally used as pulse instruction, i.e. SFWRP.

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(% class="table-bordered" %)

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|(% rowspan="2" %)**Operands**|(% colspan="4" %)**Bit device**|(% colspan="12" %)**Word device**

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|X|Y|M|S|K|H|E|KnX|KnY|KnM|KnS|T|C|D|V|Z

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|S| | | | |√|√| |√|√|√|√|√|√|√| |

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|D| | | | | | | | |√|√|√|√|√|√| |

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|n|(% colspan="16" %)Constant, 2≤n≤2048

**Program example**

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[[image:7-8 Rotation and shift_html_6f98d71fd24cc66c.jpg||class="img-thumbnail" height="163" width="600"]]

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When X0 is triggered, the contents of D0 are stored in D2, and the contents of D1 become 1. While X0 is turned from OFF to ON, the contents of D0 are stored in D3, and the contents of D1 become 2, and so on. If the contents of Dl exceed n-1, the instruction is not processed and the carry flag M8022 is set to 1

Wiki source code of 09 Rotation and shift

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