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06 High-speed counter

Last modified by Mora Zhou on 2023/11/21 14:33

Specifications of high-speed counter

Types of high-speed counters

(1) Single-phase input counter (S/W)

The counting method of single-phase input counter (S/W) is as follows:

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(2) AB phase input counter [1 times frequency]

The counting method of AB phase input counter [1 times frequency] is as follows:

Increase/decrease actionTiming
When counting upPhase A input is ON and phase B input is OFF→ON, the count will increase by 1
When counting downWhen the A phase input is ON and the B phase input is ON→OFF, the count will decrease by 1

When counting up When counting down

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(3) AB phase input counter [2 times frequency]

The counting method of 2-phase 2-input counter [2 times frequency] is as follows:

Increase/decrease actionTiming
When counting up

When the A phase input is ON and the B phase input is OFF→ON, the count will increase by 1;

The count will increase by 1 when the phase A input is OFF and the phase B input is ON→OFF.

When counting down

When A phase input is ON and B phase input is ON→OFF, the count will decrease by 1;

When phase A input is OFF and phase B input changes from OFF→ON, the count will decrement by 1.

When counting up When counting down

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(4) AB phase input counter [4 times frequency]

The counting method of 2-phase 2-input counter [4 times frequency] is as follows:

Increase/decrease actionTiming
When counting up

When B phase input is OFF and A phase input is OFF→ON, the count will increase by 1;

When the A phase input is ON and the B phase input is OFF→ON, the count will increase by 1;

When B phase input is ON and A phase input is ON→OFF, the count will increase by 1;

The count will increase by 1 when the phase A input is OFF and the phase B input is ON→OFF.

When counting down

When A phase input is OFF and B phase input is OFF→ON, the count will decrease by 1;

When B phase input is ON and A phase input is OFF→ON, the count will decrease by 1;

When A phase input is ON and B phase input is ON→OFF, the count will decrease by 1;

When Phase B input is OFF and Phase A input is ON→OFF, the count will decrement by 1.

When counting up When counting down

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Highest frequency

The maximum countable frequency of various high-speed counters is as follows:

Counter typeHighest frequency
Single phase input counter (S/W)150KHz
AB phase input counter [1 times frequency]100KHz
AB phase input counter [2 times frequency]100KHz
AB phase input counter [4 times frequency]100KHz

Counting range: -2147483648 to 2147483647, which is a signed 32-bit ring counter.

High-speed counter allocation

The input soft components of various types of high-speed counters are fixedly allocated, including 8 channels HSC0 to HSC7.

Each channel can be changed to single-phase input or AB-phase input according to the high-speed counter configuration, but it should be noted that the occupied X point cannot be repeated.

ChannelHigh-speed counter typeX0X1X2X3X4X5X6X7X10X11X12X13X14X15X16X17
HSC0Single phase input (S/W)A               
AB phase inputAB              
HSC1Single phase input (S/W) A              
AB phase input  AB            
HSC2Single phase input (S/W)  A             
AB phase input    AB          
HSC3Single phase input (S/W)   A            
AB phase input      AB        
HSC4Single phase input (S/W)    A           
AB phase input        AB      
HSC5Single phase input (S/W)     A          
AB phase input          AB    
HSC6Single phase input (S/W)      A         
AB phase input            AB  
HSC7Single phase input (S/W)       A        
AB phase input              AB

A: Phase A input B: Phase B input

✎Note: After HSC0 uses the AB phase input, HSC1 can no longer use single-phase input, because HSC0 occupies two points X0 and X1, and if HSC1 wants to use single-phase input, X1 needs to be occupied and conflicts occur. The same is true for other channels.

High-speed counter use steps

The following describes the steps to use the high-speed counter.

“Project management” → “Parameter” → “High-speed counter configuration”

(1) Screen display

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(2) Display content

ParameterRangeInstructionDefaults
Use or notUse/not useSet whether to use the counter.Unused

Pulse input

mode

Single phase input

AB phase input

Choose to use single phase input or AB phase inputSingle phase input
Counting directionUp counting mode down counting modeSelect up/down counting mode, valid only when single-phase inputUp counting mode
Frequency multiplication

One times frequency

two times frequency

four times frequency

Select input count multiplier, only valid when AB phase inputOne times frequency
Input frequency test time (ms)1 to 32767(ms)Set how often the input frequency is measured at the interval. The shorter the set time, the less accurate the frequency. The frequency measurement result is output in the special register SD. For details, see the description of the SD high-speed counter in the special register.1000ms
Filter time0 to 1700(0.01us)

Set the X point of this channel as the filter time for high-speed input. The smaller the filter setting, the more accurate the theoretical count, but the anti-interference ability will be reduced (the filter time is only valid for unidirectional input).

When the input is 0, it is the lowest filter time supported by the system.

1
Highest frequency

Single phase input: 150K

AB phase input: 100K

Display the highest input frequency that each channel can reach, read only 
Occupy X points-Show which X points are occupied after using the channel, read only 
Check button Check whether the configured X input point is reused, it is recommended to click check when setting is completed, and then confirm the input 
Restore to default Restore to the same default settings as above 
Input (X) description Pop up the description table of all modes of each channel occupying X 
Confirm input After the configuration is complete, click to confirm the input to save the configuration and take effect 

(3) Configuration example

HSC0 to HSC3 are configured as 4 single-phase inputs, and HSC4 to HSC7 are configured as 4 AB phase inputs.

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Use the OUT HSC instruction in the main program to enable High-speed counter. At this time, as long as there is an external pulse input, the pulse value can be observed in HSC0 to HSC7.

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In the double word composed of special soft components SD403 and SD402, the current input pulse frequency of HSC0 can be monitored. Other channels also have corresponding registers, please refer to the description of special registers for details.

If the counter need to be stopped, just turn off the OUT HSC instruction.

High-speed counter instructions

OUT HSC/High-speed counter switch

 When the operation result before the OUT HSC instruction is ON, the high-speed counter is turned on. At this time, the value of the HSC register records the number of high-speed pulses currently received. If the count value is reached, the corresponding HSC bit register becomes on.

-[OUT (d) (value)]

Content, range and data type

ParameterContentRangeData typeData type (label)
(d)High-speed counter channelHSC0 to HSC7Signed BIN 32 bitANY32
(value)High-speed counter setting value-2147483648 to 2147483647Signed BIN 32 bitANY32

Device used

InstructionParameterDevicesOffset modification

Pulse

extension

KnXKnYKnMKnSDRSDHSCK[D]XXP
OUT HSCParameter 1       ●   
Parameter 2●●●●●●● ●  

Features

To enable or disable high-speed counter counting, please configure the high-speed input channel to use the high-speed counter. For details, refer to the high-speed counter description.

Operation result before instructionActionHSC data register statusHSC bit register status
ONTurn on High-speed counterThe value is accumulated according to the input pulseTurn ON when the value reaches the set value, otherwise OFF
OFFStop High-speed counterThe value remains the sameState remains unchanged

Error code

Error codeContent
4085H(value) The read address exceeds the device range
2580HAfter the high-speed counter is turned on, but the axis high-speed counter enable is not configured

Example

HSC0 to HSC3 are configured as 4 single-phase inputs, and HSC4 to HSC7 are configured as 4 AB phase inputs.

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Use the OUT HSC instruction in the main program to enable High-speed counter. At this time, as long as there is an external pulse input, the pulse value can be observed in HSC0 to HSC7.

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In the double word composed of special soft components SD403 and SD402, the current input pulse frequency of HSC0 can be monitored. Other channels also have corresponding registers, please refer to the description of special registers for details.

When the value of HSC0 is greater than 0, the contact of HSC0 will be set, and the other channels are the same. As shown in the circuit program below, Y0 will be turned on.

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DHSCS/High-speed comparison set

 Comparing the counted value in the high-speed counter with the specified value each time it counts, and then immediately set the bit device instruction.

-[DHSCS (s1) (s2) (d)]

Content, range and data type

ParameterContentRangeData typeData type (label)
(s1)The data compared with the current value of the high-speed counter, or the word device number where the data to be compared is stored-2147483648 to +2147483647Signed BIN 32 bitANY32
(s2)High-speed counter deviceHSC0 to HSC7Signed BIN 32 bitANY32
(d)Bit device number set (ON) when they match BitANY_BOOL

Device used

InstructionParameterDevicesOffset modification

Pulse

extension

YMSSMD.bKnXKnYKnMKnSDRSDLCHSCKH[D]XXP
DHSCSParameter 1     ●●●●●●●●●●●● 
Parameter 2             ●    
Parameter 3●●●●●             

Features

• When the current value of the high-speed counter of the channel specified in (s2) becomes the comparison value (s1) (in the case of the comparison value K200, 199→200 and 201→200), regardless of the scan time, the bit device (d) Both will be set (ON). This instruction performs comparison processing after the counting processing of the high-speed counter.

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• If the device specified in (d) is Y0 to Y20, when (d) is set, Y will be directly mapped to the actual hardware output, regardless of the scan cycle.

• DHSCS parameter 3 can also use the interrupt function name as a parameter. As shown in the figure below, the interrupt program INT0 will be executed when HSC0 is from (19999→20000) or (20001→20000).

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✎Note: 

The high-speed counter interrupt only supports a total of 100 programs, and each DHSCS is also counted in these 100. If it exceeds, an operation error will be reported.

Error code

Error codeContent
4084HThe input device in (s2) exceeds the range of HSC0 to HSC7
4085H(s1) and (s2) read addresses exceed the device range
4086H(d) write address exceeds the device range
2406HThe number of high-speed counter interrupts exceeds 100
4F81HDHSCS,SHSCR and DHSZ runs,but OUT HSC does not program

Example

To configure the high-speed counter, take HSC0 as an example.

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In scanning MAIN, use the EI instruction to enable the interrupt, and then use the OUT HSC instruction to turn on the high-speed counter.

After M0 is turned on, when the value of HSC0 changes from 19999→20000, the INT0 program is executed once, that is, D0 is increased by 1.

When the value of HSC0 changes from 20000→20001, the INT0 program is not executed, that is, D0 remains at 1.

When the value of HSC0 changes from 20001→20000, the INT0 program is executed once, that is, D0 is increased by 1, and D0 is 2.

DHSCR/High-speed comparison reset

Each time it counts, compare the counted value in the high-speed counter with the specified value, and then immediately reset the bit device instruction.

-[DHSCR (s1) (s2) (d)]

Content, range and data type

ParameterContentRangeData typeData type (label)
(s1)The data compared with the current value of the high-speed counter, or the word device number where the data to be compared is stored-2147483648 to 2147483647Signed BIN 32 bitANY32
(s2)High-speed counter deviceHSC0 to HSC7Signed BIN 32 bitANY32
(d)Bit device number reset (OFF) when they match BitANY_BOOL

Device used

InstructionParameterDevicesOffset modification

Pulse

extension

YMSSMD.bKnXKnYKnMKnSDRSDLCHSCKH[D]XXP
DHSCRParameter 1     ●●●●●●●●●●●● 
Parameter 2             ●    
Parameter 3●●●●●             

Features

• When the current value of the high-speed counter of the channel specified in (s2) becomes the comparison value (s1) (in the case of the comparison value K200, 199→200 and 201→200), regardless of the scan time, the bit device (d) Both will be reset (OFF). This instruction performs comparison processing after the counting processing of the high-speed counter.

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• If the device specified in (d) is Y0 to Y20, when (d) is set, Y will be directly mapped to the actual hardware output, regardless of the scan cycle.

✎Note: 

The high-speed counter interrupt only supports a total of 100 programs, and each DHSCR is also counted in these 100. If it exceeds, an operation error will be reported.

Error code

Error codeContent
4084HThe input device in (s2) exceeds the range of HSC0 to HSC7
4085HThe (s1) and (s2) read addresses exceed the device range
4086HThe (d) write address exceeds the device range
2406HThe number of high-speed counter interrupts exceeds 100
4F81HDHSCS,SHSCR and DHSZ runs,but OUT HSC does not program.

Example

To configure the high-speed counter, use HSC0 as an example.

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Use the OUT HSC instruction to turn on the high-speed counter while scanning MAIN.

After M0 is turned on, when the value of HSC0 changes from 99→100, reset Y0 and D0 will increase by 1.

DHSZ/High-speed zone comparison

The current value of the high-speed counter is compared with two values (bandwidth), and the comparison result is output.

-[DHSZ (s1) (s2) (s3) (d)]

Content, range and data type

ParameterContentRangeData typeData type (label)
(s1)The data compared with the current value of the high-speed counter, or the word device number (comparison value 1) where the data to be compared is stored-2147483648 to 2147483647Signed BIN 32 bitANY32
(s2)The data compared with the current value of the high-speed counter, or the word device number (comparison value 2) where the data to be compared is stored-2147483648 to 2147483647Signed BIN 32 bitANY32
(s2)High-speed counter deviceHSC0 to HSC7Signed BIN 32 bitANY32
(d)The device number of the start bit of the comparison result output in comparison value 1 and comparison value 2 Bit

ANYBIT_ARRAY

(number of elements: 3)

Device used

InstructionParameterDevicesOffset modification

Pulse

extension

YMSSMD.bKnXKnYKnMKnSDRSDLCHSCKH[D]XXP
DHSCZParameter 1     ●●●●●●●●●●●● 
Parameter 2     ●●●●●●●●●●●● 
Parameter 3             ●    
Parameter 4●●●●●             

Features

• Compare the current value of the high-speed counter specified in (s3) with two comparison values (comparison value 1, comparison value 2), regardless of the scan time, (d), (d)+1, (d)+2 One item in will turn ON according to the comparison result (lower, in area, upper).

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• If the device specified in (d) is Y0 to Y15, when (d), (d+1), (d+2) are set, Y will be directly mapped to the actual hardware output, not affected by the scan cycle .

• When setting [Comparison Value 1] and [Comparison Value 2], please ensure that [Comparison Value 1]<[Comparison Value 2]. If the settings are different, an operation error will occur, and the DHSZ instruction will not execute the action.

✎Note: 

The high-speed counter interrupt only supports a total of 100 programs, and each DHSZ is also counted in these 100, and the DHSZ instruction will occupy the space of 2 interrupt programs. If it exceeds, an operation error will be reported.

The comparison result occupies the unit of 3 consecutive addresses starting with (d). Please be careful not to overlap with other controlled devices. In addition, when specifying the Y device, please set it not to exceed the actual number of Y point outputs.

Error code

Error codeContent
4084H(s2) The input device exceeds the range of HSC0 to HSC7
4085H(s1)(s2) The read address exceeds the device range
4086H(d) The write address exceeds the device range
2406HThe number of high-speed counter interrupts exceeds 100
4F81HDHSCS,SHSCR and DHSZ runs,but OUT HSC does not program

Example

To configure the high-speed counter, use HSC0 as an example.

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Scanner

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Execution results

Comparison modeCurrent value of channel 1 (s3)Change of output contact (Y)
Y0Y1Y3
(S1)>(s3)1000>(s3)ONOFFOFF
999→1000ON→OFFOFF→ONOFF
1000→999OFF→ONON→OFFOFF
(S1)≤(s3)≤(s2)999→1000ON→OFFOFF→ONOFF
1000→999OFF→ONON→OFFOFF
1000≤(s3)≤2000OFFONOFF
2000→2001OFFON→OFFOFF→ON
2001→2000OFFOFF→ONON→OFF
(S3)>(s2)2000→2001OFFON→OFFOFF→ON
2001→2000OFFOFF→ONON→OFF
(S3)>2000OFFOFFON